I. Introduction
In recent years, wireless power transfer (WPT) and energy harvesting (EH) technologies have gained immense popularity for application in the power-charging systems of electronic devices where wired power transfer is infeasible or difficult to deploy [1, 2].
Microwave rectifiers are one of the key components employed to convert AC power into DC power that prioritizes high power conversion efficiency (PCE) in rectifier designs [3]. For single-band (SB) operations, harmonic control techniques, such as class F [4–7], inverse class F [8–10], class C [11, 12], class R [13, 14], and power recycling [15, 16], have been commonly applied to reduce diode loss and, in turn, maximize PCE. Typically, these methods require precise harmonic termination up to the third order.
Dual-band (DB) rectifiers have attracted a lot of attention not only as a solution to the trade-off between peak PCE and bandwidth in EH systems but also as a means to ensure flexibility in WPT systems, enabling the transmission of power at two frequencies depending on power availability [17, 18]. However, the design process of a DB rectifier is challenging and complicated owing to the concurrent need for precise DB harmonic and fundamental matchings. Conventional approaches rely on a topology that integrates a DB harmonic control network (DB-HCN) with a DB fundamental matching network (DB-FMN) in a separate arrangement [19–25]. These networks usually follow the same configuration as their single-frequency counterparts, extending their corresponding functional blocks for DB operations (see Fig. 1). However, this configuration has certain drawbacks: (i) high design complexity and (ii) lack of frequency freedom, i.e., inability to design two frequencies with an integer ratio. Recently, efforts have been made to reduce design complexity either by reversing the order of the functional blocks using a DB resonator [26] or by utilizing a two-in-one integration network [27]. Nevertheless, these methodologies have been unable to resolve the problem of frequency limitation, while harmonic and fundamental matchings have continued to exhibit sensitive behavior in practical realization owing to the use of cascaded DB networks.
In this study, a novel approach for designing a DB harmonic-controlled rectifier that offers high design feasibility and frequency-unconstrained properties is introduced. The proposed structure involves splitting the total input power using a 3-dB branch-line coupler, which is then used to excite the harmonic-controlled sub-rectifiers configured using conventional SB networks (DB operation conducted using only SB networks). Each sub-rectifier is optimized to operate at a specific frequency while preventing rectification at another frequency. Furthermore, to compensate for the 3-dB power loss at the coupler’s outputs and ensure optimal PCE achievement at each frequency, the isolation port of the coupler is grounded, resulting in an efficient reflection mechanism that returns the missing power to the main sub-rectifier for another round of rectification. This serves to enhance the DC output power as well as the PCE, which finally reaches its optimal value, as recorded when using SB rectifiers. In the proposed design, the rectifier exhibits low design complexity and is independent of frequency. For verification, a pair of frequencies—f1= 0.915 GHz and f2 = 1.83 GHz (f2=2f1)—were selected, representing a constrained scenario for conventional DB structure-based designs. The component parameters were extracted without applying any tuning mechanism. The measurement results showed optimal peak PCE of 77.4% and 77.1% at the two frequency bands.
II. Disadvantages of Conventional Designs
The conventional design of a DB rectifier with harmonic control is depicted in Fig. 1, where the DB-HCN is designed separately from the DB-FMN. Usually, the DB-HCN is implemented first. It can be located either at the cathode of the diode (Type I [19, 22]), at the anode of the diode (Type III [23, 25]), or on both diode sides (Type II [20, 21]), as sketched in Fig. 1. The input impedance Zin, which is a combination of the diode- and DB-HCN-induced impedances, is used to perform fundamental matching with a specific network. A number of fundamental DB matching topologies based on transmission lines (TLINs) are presented in Fig. 2. These circuits share the same operating principle by which Tm converts the impedance value of Zin at two design frequencies into a conjugated pair of impedances before meeting the DB matching condition using the other TLINs. Assuming Zin@f1=R1+jX1 and Zin@f2=R2 +jX2 are the complex impedance values of Zin at frequencies f1 and f2, respectively, the characteristic impedance (Zm) and electrical length (θm) of Tm can be extracted using the following equations:
where k=f2/f1, and n is an arbitrary integer. Although the conventional design approach successfully yields high-efficiency DB operation for certain specifications, it has two main disadvantages:
1) Low design realizability
DB-HCN and DB-FMN need a highly complex multi-stage TLIN configuration, which often makes the combined input impedance Zin uncontrolled at the fundamental frequencies. This may prevent the realization of the DB-FMN based on Eqs. (1) and (2) since Zm is not ensured a positive value. As a result, the possibility of successful design realization using the traditional method is low. One can introduce an extra line to tune Zin into its proper values, as depicted in Fig. 2(e). However, in most cases, this method is found to be time-consuming and inefficient.
2) Constrained operating frequency
The typical harmonic termination classes, such as class C, class F, inverse class F, and class R, commonly force harmonics with either zero, infinite, or purely reactive impedance [4–14]. In the case of a pair of frequencies with an integer relation, such as f2=kf1, k=2,3…, where f2 is the harmonic component of f1, it becomes impossible to match Zin (which is either zero, infinity, or purely reactive at f2) to the source RS at f2. In other words, the conventional structure is not capable of yielding optimal DB operation at these frequencies.
In the next section, a different approach for realizing the DB operation of a rectifier is presented, which overcomes the drawbacks of conventional designs while also ensuring that optimal PCE is achieved.
III. Proposed Structure and Analysis
The proposed structure, illustrated in Fig. 3, consists of a 3-dB DB branch-line coupler whose two output ports are connected to a rectifier branch that is optimized to function at one of the design frequencies. The DB operation of the coupler aims to concurrently satisfy an equal power split at f1 and f2. The sub-rectifier helps implement only single-band HCN (SB-HCN) and single-band FMN (SB-FMN), indicating a simpler procedure than the DB networks employed in traditional architectures. Assuming that the upper and lower branches are designed to optimally rectify the AC signal at f1 and f2, respectively, it is easy to see (initial estimation) that if the upper SB-FMN remains perfectly matched at f1 while being completely mismatched at f2, and vice versa in the case of the lower SB-FMN, DB operation would be achieved. However, since the power at the coupler’s output ports is reduced by 3 dB, a non-trivial PCE degradation takes place, due to which the achievable PCE is not optimal. This problem is addressed by the reflection mechanism of the branch-line coupler, formulated by grounding its isolation terminal, as shown in Fig. 3. Consequently, the reflection coefficients induced by the upper and lower SB-FMNs are optimized until optimal PCE is achieved. The detailed operating principle for achieving the optimal PCE is described in the next subsection.
1. Operating Principle for Optimal PCE Achievement
To analyze the working principle for optimal PCE attainment, the proposed topology is simplified into several steps, as shown in Fig. 4, where Zin1 and Zin2 are the impedances induced by the sub-rectifier paths. Assuming that the overall rectifier operates at f1 at a given power level, it is considered that the input signal s1, defined as s1 = Asin(ωt+ϕ), is transmitted to Port 1 of the coupler. Meanwhile, the wave transmitted to Ports 2 and 3 is given according to [5, 28].
A mismatch between the terminals (Zin1 and Zin2) and the coupler’s output ports results in reflected waves, as illustrated in Fig. 4(b). This can be expressed as follows:
where Γ1and Γ2 are the respective reflection coefficients of the two sub-rectifiers at a specific power level. These reflected waves are delivered to Ports 1 and 4 of the coupler. This procedure can be formulated as follows:
By grounding Port 4 (isolation port) of the coupler, the entire power r4 is re-injected into the coupler outputs and then into the two sub-rectifiers, as shown in Fig. 4(c), where:
This reflection procedure is repeated infinitely with the change in the reflection coefficients of Ports 2 and 3 due to the decrease in power level, as illustrated in Fig. 4(d). The reflected waves r7 and r8 can be calculated as follows:
The overall reflection coefficient can be expressed as follows:
In addition, the total electromagnetic wave power transmitted to each sub-rectifier can be formulated as follows:
Eqs. (7) and (11) imply a reduction in the wave magnitude after each reflection order, with the power fraction of r3 being the main factor determining the total reflection coefficient Γt. By optimizing Γ1 and Γ2, and due to the destructive property of (Γ2–Γ1), Γt may exhibit an acceptable value, and the overall rectifier remains matched. This is achieved by adding SB-FMNs to each sub-rectifier. In addition, owing to the reflection mechanism, the power is reinjected into the rectifier in Branch 1 at f1 (see Eq. (14)), even when there is perfect matching with Γ1=0. This compensates for the PCE degradation caused by the 3-dB power loss at the coupler output, thereby improving the PCE, which reaches an optimal value. For efficient rectification with harmonic control at f1, the rectifier in Branch 2 should exhibit a complete mismatch at f1, i.e., Γ2@f1=1 and Γ1@f1 does not need to be zero, as previously estimated, but it can be much less than 1. The power loss due to the 3-dB coupling drop and the slight mismatch at f1 of the rectifier in Branch 1 is recovered by the wave reflection mechanism, as described above. This process also occurs at the f2 frequency operation of the rectifier, with Γ1@f2=1 and Γ2@f2 ≪ 1. Finally, the total power delivered to the lower sub-rectifier is described by Eq. (15).
2. Frequency-Unconstrained DB Branch-Line Coupler Design
In the proposed structure, a DB branch-line coupler is used to ensure precise operation of the reflection mechanism at each design frequency. Notably, a DB branch-line coupler can be realized in many ways [29–32]; however, it must exhibit a frequency-unconstrained characteristic. To achieve this, a port-extension version, as shown in Fig. 5, is employed due to its frequency-unlimited calculations. Assuming Zi and θi are the characteristic impedance and electrical length of TLIN Ti (i=1, 2, 3), respectively, the normalized characteristic impedances can be expressed as follows [30]:
where θ1=θ2=θ3=θ0, which can be calculated as follows:
or
3. DC-Pass Filter Realization
Fig. 3 shows that each sub-rectifier is equipped with an RF choke, which forms a DC-pass filter at the load. The RF choke is necessary to block the AC signal at all frequencies, thereby avoiding power leakage without rectification. Although high-inductance inductors are generally utilized as RF chokes, they also exhibit low self-resonant frequency (SRF), which leads to unwanted behaviors, especially at higher-frequency bands.
Given f1<f2, a high-inductance inductor may lead to a spurious AC-signal choke at f2, whereas a low-inductance inductor may yield insufficiently high impedance to effectively block the AC signal at f1. To address this issue, a method to realize a quasi-ideal DC-pass filter was employed in the proposed circuit. As shown in Fig. 6, Branch 1 comprises an inductor with high inductance L1 for choking the f1 signal. Notably, the value of L1 was selected as high as possible in the inductor models so that its SRF would be at least higher than f1. Next, a f2 bandstop filter cascaded by a λ/4 TLIN and a λ/4 radial stub at f2 is added to suppress the f2 signal. The impedance ZL was calculated at f1 and f2 using the following equations:
where Z0 refers to the characteristic impedance of the λ/4 stub and ZL1@f2 denotes the impedance induced by L1 at f2. Notably,
Z M upper @ f 1 ≪ 2 π f 1 L 1
4. HCN and FMN Design
For efficient rectification, proper harmonic control was ensured by considering several types of structures, as depicted in Fig. 1. Ideally, an infinite number of harmonics need to be terminated to minimize diode loss and obtain the maximum PCE. However, it has already been demonstrated that optimal PCE can be achieved only through up-to-third-order harmonic manipulation [4]. The sub-rectifier employed in this study contains only SB-HCNs, which can be easily realized using simple networks, such as inverse class F, class F, or class C SB circuits, as investigated in [4, 8, 11]. An inverse class F-based termination with Type-II configuration [8] is deployed, since it has the simplest implementation—a λ/8 TLIN was added at the diode anode for open termination at the second harmonic, and an open λ/12 stub was connected at the diode cathode for short termination at the third harmonic. As discussed in Section III-1, the SB-FMN of each rectifier branch plays an important role in ensuring an efficient reflection mechanism. The SB-FMNs had to be designed in a way that allowed the upper branch to fully isolate the AC signal at f2 and the lower branch to block the AC signal at f1 entirely. This condition was satisfied using the following design process: first, a common L-type matching network was designed to match the input impedance (the combined impedance of the diode and SB-HCN, extracted based on source–pull simulation at a specific power level) to the output impedance of the coupler (50 Ω) at f1 for Sub-rectifier 1 and at f2 for Sub-rectifier 2. Next, the two SB-FMNs were inserted into the overall schematic together with the diode model, and an optimization scheme was performed until the target performance was achieved using fabrication-feasible TLIN parameters.
IV. Implementation and Experiment
To further verify the effectiveness of the proposed design, a frequency pair of f1=0.915 GHz and f2=1.83 GHz, with a ratio of k=f2/f1=2, was selected. Notably, this frequency pair is one of the constrained specifications for conventional structures. The overall schematic of the design is shown in Fig. 7, while the TLIN parameters for optimal DB operation are listed in Table 1.
A photograph of the fabricated prototype is provided in Fig. 8, while Fig. 9 demonstrates the standalone DB characteristics of the coupler based on its S-parameters (magnitude and phase). As expected, S21 and S31 are −3 dB, and their phase difference is 90° at both frequency bands.
The total reflection coefficient S1 (or Γt) corresponding to the frequency at the input port of the overall rectifier is presented in Fig. 10, showing that the two extremal values of S1 occurs at the two target frequencies in the simulation. Furthermore, <−18 dB implies that most of the input power was delivered to the sub-rectifiers for rectification, as predicted in Eq. (13), through the destructive property of the reflection mechanism. The measured S1 exhibits a similar behavior to the simulation results, except for the slight shift in frequency at both frequency bands—the extremal points are recorded at 0.912 GHz and 1.866 GHz. Note that the load resistors RL for estimating the optimal measured and simulated performance were determined to be 620 Ω and 600 Ω, respectively.
Fig. 11 presents the measurement setup for the experimental verification of the rectifier in terms of output voltage and PCE. The RF signal was generated by a signal generator and then transferred through a coupler to the rectifier device. The precise power level at the rectifier’s input was evaluated based on the coupling power of the coupler using a spectrum analyzer. Subsequently, the output voltage was measured using a DC meter. Finally, the corresponding PCE was calculated based on the following equation:
Fig. 12 shows the simulation and measurement results obtained with regard to variations in frequency. The results show that the peak PCE is 76.4% at 0.915 GHz and 74.9% at 1.83 GHz, with the input power being 8.5 dBm. The measured PCE was extracted at 10-dBm input power, exhibiting 74.4% and 77.0% at 0.912 GHz and 1.866 GHz, respectively.
Fig. 13 illustrates the simulated DC branch current of each sub-rectifier with respect to the frequency at an input power of 10 dBm. It is observed that the total DC output current at f1 is generated entirely by the AC–DC conversion of the rectifier in Branch 1. Meanwhile, only the DC current idc2 in the rectifier in Branch 2 contributes to the optimal PCE at f2. Moreover, there is no co-existence of idc1 and idc2 at the two frequency bands, implying an absolute blocking characteristic yielded by the SB-FMN of each sub-rectifier to the off-branch frequency, as emphasized in the analysis conducted in Section III-1. This also implies that the power-returning mechanism of the coupler works properly, boosting the output current of each sub-rectifier to reach the optimal value at each target frequency.
The results obtained for the PCE and output voltage with regard to the input power are provided in Figs. 14 and 15 for the first and second frequency bands, respectively. For the f1 band, peak PCE of 77.4% and 76.8% was achieved for the measurement and the simulation, respectively, at an input power of 8.5 dBm, corresponding to an output voltage of 1.74 V and 1.71 V, respectively. In the case of the second band, the PCE peaked at 77.1% for the measurement and at 76.6% for the simulation at an input power of 10 dBm. Notably, the PCE reduction observed at the higher power levels matched the saturation of the output voltage. Overall, the measurement and simulation results agree well. Fig. 16 displays the variations in the measured PCE according to the load resistance at 10 dBm input power, showing that PCE increases with an increase in RL for both design frequencies until the peak value is reached at 620 Ω.
A comparison of the proposed rectifier with several previously reported DB designs is summarized in Table 2. It is evident that the proposed rectifier is the first design to utilize simple SB-HCNs and SB-FMNs to realize DB operations while achieving optimal PCE comparable to other designs. Moreover, an integer ratio of frequency is allowed in the proposed structure, which addresses a common limitation of existing networks, highlighting the design’s high flexibility of frequency.
V. Conclusion
This paper introduces an alternative structure for realizing a DB rectifier that offers a number of advantages over conventional designs, such as high realizability and frequency independence, while also maintaining optimal PCE. This achievement is made possible by the reflection mechanism of the branch-line coupler, which repeatedly injects missing power back for rectification instead of returning it to the source. The proposed approach was verified using a rectifier design at 0.915 GHz and 1.83 GHz—frequencies that are constrained in conventional designs—achieving optimal PCE at both bands (77.4% and 77.1%) using only single-band HCNs and FMNs.
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