A broadband high-power amplifier (HPA) monolithic microwave-integrated circuit (MMIC) is a critical component in electronic warfare, radar, and communication systems [1, 2]. Owing to the commercialization of 5G, 6G, and satellite communications, the demand for broadband HPA MMICs has increased significantly [3, 4]. In this regard, driven by advancements in GaN HEMT MMIC processes, non-uniform distributed power amplifiers (NDPAs) are being actively researched with the aim of achieving high power over a wide bandwidth [5–7].

Impedance transformers are essential for the output matching of NDPAs. They match the low output impedance of power amplifiers to 50 Ω. Ruthroff impedance transformers, in particular, have attracted attention due to their relatively high transform ratio of 4:1, wide bandwidth characteristics, and their ability to be integrated into bias circuits without the need for a bulky choke inductor [8, 9].

To incorporate Ruthroff impedance transformers into wideband HPA MMICs, it is necessary to design the transformer as an asymmetrical structure capable of handling the large currents associated with high output power (P_out). However, while considerable research has been conducted on asymmetric coupled lines and symmetric impedance transformers, studies on asymmetric Ruthroff impedance transformers remain limited [10–12]. In this study, theoretical formulas and analyses for designing an asymmetric Ruthroff impedance transformer are presented. Subsequently, the asymmetrical impedance transformer is fabricated using a commercial MMIC process, and its performance is verified through application in a 6–18 GHz NDPA.

The design of a conventional impedance transformer is simply based on the assumption that its two coupled lines have the same width, which makes it relatively simple to analyze and easy to implement. However, when one of the coupled lines is used to supply drain bias current, its width is bound to increase. If both lines are widened, the size becomes too large for implementation in a planar structure, leaving no choice but to introduce an asymmetrical coupled-line structure.

To derive the equation for the asymmetric Ruthroff impedance transformer, we relied on formulas proposed for four-port asymmetrical coupled transmission lines and symmetrical Ruthroff impedance transformers in previous studies [11, 13]. Fig. 1(a) illustrates a typical asymmetric coupled line structure, while Fig. 1(b) depicts an asymmetric Ruthroff impedance transformer implemented using this structure. This transformer was realized as a two-port structure by connecting Port 2 and Port 4 of the four-port asymmetric coupled line structure and grounding Port 3, as shown in Fig. 1(b). For clarity, the parameters of the four-port coupled line are denoted in lowercase, and those of the two-port impedance transformer are denoted in uppercase. The Y-parameters for Fig. 1(a) can be expressed as follows [11]:

where Y_e1, Y_e2, Y_o1, and Y_o2 denote the characteristic admittances of Lines 1 and 2 for even and odd modes, respectively, while γ_e and γ_o are the propagation constants for even and odd modes, respectively. Furthermore, R_e and R_o refer to the ratio of wave voltages of the two lines for even and odd modes, respectively, and l is the length of the lines.

Based on the above formulas, the Y-parameters for the two-port structure in Fig. 1(b) were calculated. First, drawing on the definition of Y-parameter, the following 4 × 4 matrix was constructed for the four-port coupled line:

Assuming that the line connecting Ports 4 to 2 in Fig. 1(b) is short enough to not affect the phase change, the following terminal conditions were considered for the structure in Fig. 1(b): v₁ = V₁, v₂ = v₄ = V₂, v₃ = 0, i₁ = I₁, and i₂ + i₄ = I₂. Upon applying these relations to Eq. (1), it was recalculated in terms of V₁, V₂, I₁, and I₂, as follows:

Eqs. (8)–(9) can be expressed in matrix form as follows:

Drawing on the matrix in Eq. (10)Y-parameters of the asymmetric Ruthroff impedance transformer were obtained using the Y-parameters of the asymmetric coupled line, as expressed in Eqs. (1)–(6). Eqs. (11)–(14) denote the Y-parameters of the Ruthroff impedance transformer.

Fig. 2 presents a schematic of the output circuit upon employing an impedance transformer in a broadband HPA. It indicates that the final equation required for impedance transformer design is that of the output impedance (Z_out), as observed at the output end of the power amplifier for the output load admittance Y_L (or load impedance Z_L) [11]. Therefore, to determine Z_out, we first derived Y_L from the Y-parameters of the impedance transformer, which we calculated using the equations mentioned above, and then expressed Z_out in terms of Y_L and the Y-parameters based on the definition of Z_out. This procedure is summarized in the equations below:

Furthermore, to analyze bandwidth characteristics using the derived equations, physical information pertaining to a commercial MMIC process was substituted into the equations. First, the basic parameters of the asymmetric coupled lines—R_e, R_o, γ_e, γ_o, Y_e1,2, and Y_o1,2—were formulated as Eqs. (17)–(24), as noted below [12]:

where a₁ = y₁z₁ + y_mz_m, a₂ = y₂z₂ + y_mz_m, b₁ = z₁y_m + y₂z_m, and b₂ = z₂y_m + y₁z_m.

Notably, y₁, y₂, y_m, z₁, z₂, and z_m, which form the basis of the above equations, were first calculated based on the dielectric constant of the MMIC process, the substrate thickness, the width and thickness of each line, and the minimum spacing between each line [12–15], and then substituted into Eqs. (11)–(24). Table 1 summarizes the physical information related to the commercial MMIC process considered in this study. Notably, the data in Table 1 were provided by the GaN HEMT MMIC foundry that performed the actual fabrication. The line widths were empirically selected based on the width range of the lines commonly used in the actual layout of impedance transformers, and the minimum line spacing was based on the design-rule checking (DRC) rules set by the foundry.

Figs. 3 and 4 show the real and imaginary parts of Z_out as functions of βl. Fig. 3(a) and 3(b) illustrate the variation in Z_out as the width of Line 1 (w₁) increases from 10 to 100 μm, with the width of Line 2 (w₂) and the line spacing (s) set at 10 μm. It is observed that both the real and imaginary parts of Z_out change gradually with βl as w₁ increases. Fig. 4(a) and 4(b) present the variation in Z_out as w₂ increases from 10 to 100 μm at w₁ = 10 μm and s = 10 μm. Unlike the trends observed in Fig. 3(a) and 3(b), the change in Z_out as w2 increases is not as pronounced as that observed in the case of increasing w₁. Moreover, a faster change is observed for the real part when βl is below 0.7.

Notably, a slow change in the output impedance of an impedance transformer with respect to βl indicates good bandwidth performance. Therefore, based on the analysis above, it can be concluded that when designing a transformer, increasing the width of the coupled line carrying the RF signal and decreasing the width of the line supplying the bias current will enhance the bandwidth.

However, the principles outlined above cannot be applied in a straightforward manner in practical designs for HPAs, since large currents must be supplied, and a compact design is necessary to minimize the chip size. As a result, appropriate compromises need to be made.

This study presents the design of an impedance transformer for a C–Ku band NDPA. Since the line impedance at the final output stage of an NDPA is approximately 12 Ω, an impedance transform ratio of 4:1 must be ensured. Additionally, since the NDPA must operate over a wide bandwidth and provide drain bias at the output stage, a Ruthroff impedance transformer scheme that meets these requirements had to be adopted. Furthermore, to achieve an average output power exceeding 20 W, it must allow several amperes of drain current to flow. Meeting this requirement necessitates an asymmetrical structure with increased width for at least one of the two lines. In the previous section, we analyzed the effect of the width of each line on the bandwidth of an asymmetrical structure. In this section, we propose a modified structure to achieve broadband performance based on previously analyzed formulas for asymmetrical structures.

From the theoretical analysis in Section II, we concluded that when fabricating an asymmetrical Ruthroff impedance transformer, a larger width for Line 1 is a better choice, given that the width of Line 2 does not have any substantial effect on the bandwidth of the impedance transformer. However, when an impedance transformer is applied to an HPA, the width of Line 2 needs to be very large. This can be achieved by increasing the widths of both Lines 1 and 2. However, doing so would significantly enlarge the chip size, making it impossible to fabricate a planar meandered structure, which is the configuration that is typically employed. To overcome this limitation, we added shunt capacitors without increasing the width of Line 1. This addition had the same effect as increasing the width of Line 1, thus giving the impedance transformer a broadband characteristic.

Fig. 5(a) and 5(b) show the circuit schematics of a conventional symmetric Ruthroff impedance transformer and that of the proposed asymmetric one. It is evident that the proposed impedance converter is more suitable than the conventional one for HPAs that need to supply larger currents.

Fig. 6 presents the simulation results obtained for the schematics in Fig. 5(a) and 5(b). Simulations were performed using the design kit model provided in a commercial foundry. Fig. 6 clarifies that the use of shunt capacitors (Cs) reduced w₁ by one-third and halved l from 1,900 μm to 1,000 μm. Although the bandwidth has been somewhat reduced, it is an advantage that a more compact layout has been enabled while still maintaining insertion loss within 0.3 dB over the target frequencies of 6 to 18 GHz.

To further investigate the impact of the shunt capacitors, we increased the value of the Cs to simulate changes in the S₁₁ and S₂₁ characteristics of the impedance transformer. Fig. 7(a) and 7(b) illustrate the variations in S₁₁ and S₂₁ resulting from the change in C values, with the line width and line length fixed at 120 μm and 1,900 μm, respectively. It is observed that the center frequency shifts downward as the C values increase from 85 fF to 253 fF, while the bandwidth decreases as the Q value increases. This implies that, at the same operating frequency, the line length will decrease with an increase in the value of C. Furthermore, while the bandwidth will also decrease in such a case, it will be less severe than depicted in Fig. 7(a) and 7(b) if the line length is increased to match the operating frequency.

Next, we varied the line width (w₁) while maintaining the above conditions, with the Cs kept unconnected and connected. The results are presented in Fig. 8(a) and 8(b), showing that a reduction in w₁ increases the characteristic impedance, thereby increasing losses at high frequencies. However, we also observe that upon connecting the Cs, the overall bandwidth reduces, and the increase in characteristic impedance slows down with decreasing line width. This, in turn, results in a relatively small decline in S₂₁ at high frequencies. Based on the above simulation results, it can be established that to reduce the width of one of the coupled lines and to implement a compact impedance transformer by reducing the width of one coupled line and shortening the overall line length, adding Cs can be considered an effective method depending on the operating frequency band. However, it must be noted that this ease of implementation is accompanied by a proper trade-off involving increased losses at edge frequencies due to the reduced bandwidth.

For design and fabrication, Win Semiconductor’s 0.25 μm GaN HEMT MMIC process was conducted. The initial circuit layout was created using Keysight’s ADS 2016, followed by a 2.5-dimensional (2.5D) electromagnetic simulation performed using Momentum, which is supported by the same program. Subsequently, DRC and layout-versus-schematic verification were conducted using Cadence’s Virtuoso design tool, with support from the IC Design Education Center in finalizing the layout.

Fig. 9 presents the 3D structure of the designed impedance transformer. For convenience, the port numbers in Fig. 9 are reversed relative to those in the schematic in Fig. 2, and are set to match the schematic depicted in Fig. 5. The metal-insulator-metal capacitors and air bridge are also depicted in Fig. 9 for clarity. Furthermore, as assumed in Fig. 1(b), the coupled lines are configured in a meander structure to minimize the length of the connection between Ports 4 and 2, resulting in a more compact design. However, this inevitably limited the width of the coupled lines. Although a larger Line 1 (w₁, as discussed in Section II) would ideally enhance the bandwidth, it would complicate the layout in practice. Moreover, while the width of Line 2 (w₂, as discussed in Section II) should not have much of an impact on the bandwidth, its width must still be determined by accounting for the expected operating current margin, given that this line supplies the drain current. In this study, the predicted operating DC current reaches up to 1 A, while the maximum allowable DC current per micrometer supported by the MMIC process is 10 mA. Consequently, the width of Line 2 is designed to be 120 μm to accommodate the current margin and ensure layout feasibility. In contrast, since Line 1 carries RF signals, with the maximum allowable RF current being approximately 100 mA per micrometer, its width can be reduced to one-tenth that of Line 2. However, since maximizing the width of Line 1 is beneficial for the bandwidth, it was increased to 40 μm, as permitted by the meander layout.

Fig. 9 also shows that the designed impedance transformer includes additional capacitors: C1 functions as a DC block capacitor, C2 serves as a bypass or RF short in the bias circuit, and C3 and C4 are responsible for lowering the characteristic impedance (Z0) of Line 1 and achieving the effect of widening Line 1. The values for C1, C2, C3, and C4 are approximately 6.8 pF, 6.8 pF, 0.22 pF, and 0.11 pF, respectively, while the length of the coupled lines is about 930 μm. However, during actual implementation, different values were used for C3 and C4, since C4 was placed in the middle of the line due to layout constraints. Near Port 2, Line 2 crosses Line 1 through an air bridge, where the metal thickness was decreased from 3 to 2 μm. Furthermore, since the crossing of the large RF signal of Line 1 and the large DC current of Line 2 could cause the air bridge to collapse, the width of Line 1 was increased to 67 μm.

Fig. 10 presents the EM simulation results of the designed impedance transformer, acquired using ADS Momentum. Notably, the port numbers labeled in Fig. 9 also apply to Fig. 10. This means that in a real HPA design, Port 1 would be connected to the HPA output side, while Port 2 would signify the overall output port. As shown in Fig. 10, the addition of capacitors C3 and C4, as also depicted in Fig. 9, significantly improved both the S₁₁ and S₂₁ of the designed impedance transformer.

Fig. 11 shows a chip photo of the fabricated impedance transformer’s test pattern. The chip size is about 1,100 μm × 1,400 μm. Fig. 12 presents the S-parameters of the fabricated chip, measured using Anritsu’s MS4640B vector network analyzer. Notably, since the measurement setup was matched to 50 Ω, the measured S-parameter data were imported and recalculated by setting the reference impedance of Port 1 to 12.5 Ω and that of Port 2 to 50 Ω. Unlike the EM simulation environment, the actual fabricated test pattern featured an additional RF pad, while the DC pad was connected to the ground using a DC probe. Their effects resulted in measurements that were somewhat different from the EM results obtained using the pure impedance transformer circuit. The measured S-parameters in Fig. 12 indicate a decrease in bandwidth above 15 GHz, resulting in a decrease in S₂₁ compared to the simulation, although a trend similar to the simulation is largely observed. The measured S₂₁ spans −0.3 to −1.8 dB from 6 to 18 GHz, with a peak at 10 GHz. The measured S₁₁ is −5.5 to −20.4 dB from 6 to 18 GHz, with the best reflection coefficient achieved at 11 GHz.

The fabricated impedance transformer was employed in a C–Ku band NDPA MMIC. Fig. 13(a) presents the chip photo of the NDPA with the proposed impedance transformer, while Fig. 13(b) shows the P_out, power added efficiency (PAE), and gain measurement results [6]. Fig. 13(b) confirms that the proposed asymmetric impedance transformer contributes to attaining an average P_out of 20 W and a maximum P_out of 30.2 W within the 6–18 GHz range, and operates well at high output power.

Table 2 compares the performance of the proposed transformer with that of other Ruthroff impedance transformers using MMIC processes reported in the literature [16–19]. The comparison shows that unlike other transformers, the proposed impedance transformer features an asymmetrical structure that is suitable for HPAs, and achieves insertion losses that are largely at par or even better than conventional ones over an octave bandwidth.

In this study, an asymmetric Ruthroff impedance transformer for wideband NDPAs is proposed. The theory of asymmetric coupled lines is applied to derive the design formula for the asymmetric Ruthroff impedance transformer, and the impact of the widths of its two coupled lines on the bandwidth is analyzed. The fabricated impedance transformer achieved an insertion loss of less than 1.8 dB at 6–18 GHz. Furthermore, upon utilizing it in the output stage of a 6–18 GHz NDPA, an average P_out of more than 20 W was attained, demonstrating its effectiveness. Overall, the findings of this study can serve as valuable guidelines for designing asymmetric impedance transformers for wideband power amplifiers using various semiconductor processes, including GaN HEMT, GaAs HBT, and Si CMOS.