An 8-Channel Phased-Array CMOS Transmitter for 5G+ Application
Article information
Abstract
This paper presents a new 8-channel phased-array transmitter (8-CPA TX) integrated with a 10 GHz in-phase quadrature-phase (I/Q) local oscillator generator. The 8-CPA TX comprises three functionally defined subsidiary blocks—a delay-locked loop (DLL), a frequency multiplier (FM), and an 8-channel phase shifter. The DLL produces uniformly delayed 256-phase pulses when locked. When an external 156.25 MHz oscillator is applied as a reference clock, fIF is up-converted to 10 GHz by the FM. Combining the DLL and the FM in the cascade demonstrates compelling RMS jitter performance, with an integrated jitter of 72 fs from 12 kHz to 20 MHz. This is comparable to the RMS jitter of the reference clock and enables accurate I/Q signal generation. A capacitive ladder-type passive amplitude modulator (AM) is invented to implement a direct binary to millimeter wave phase shift modulation. Significant power consumption reduction is accomplished because of the no-power consumption of the AM. The proposed 8-CPA TX is implemented on the TSMC 65-nm CMOS process, with an area of 2 mm2.
I. Introduction
As the carrier frequency is increased to obtain a wide data bandwidth, propagation loss is increased to reduce the wireless communication distance. To overcome this shortcoming, extensively phased array techniques have been adopted to enhance equivalent isotropic radiated power and to provide beam-steering capability and spatial filtering [1]. A phase shifter modulator (PSM) is a core block that affects phased-array performance by enabling a wide phase-shift range, a fine phase interpolation step, and low insertion loss (IL). It can be applied to the digital, local oscillator (LO), and radio frequency (RF) domains. Active and passive RF PSM have been reported for the last decade [1–10]. A vector modulator-based active PSM, one of the most popular PSMs, consumes significant DC power, degrades accurate phase implementation due to its nonlinearity, and causes high noise figures while providing gain and a wide phase-shift range. In contrast, passive PSM burns no DC power and offers superior linearity, which is preferable for large-scale phased-array communication systems, even with high IL [6].
Some compelling passive PSM topologies have been published, such as digitally controlled transmission-line load [3], advanced switched-type architecture [8], and optimized reflection-type architecture [1, 6, 9, 10]. In the papers mentioned above, great effort has been dedicated to providing a compact die size, low IL, and high phase-shift resolution.
In addition, an LO generator beyond 5G wireless communication should achieve less than 100-fs RMS jitter for implementing more than 256-QAM data [3]. Due to the low-quality factor of the inductor as well as the capacitor at the millimeter wave (mm-wave), it is difficult to design an ultra-low phase noise (PN) LC-tuned voltage-controlled oscillator. Therefore, the cascade LO generator topology of a lower-frequency synthesizer and a frequency multiplier (FM) has been strongly recommended [11].
This paper presents a new 8-channel phased-array transmitter (8-CPA TX) integrated with a 10 GHz in-phase quadrature-phase (I/Q) LO generator. Since the proposed phase shifter is a new passive topology, the proposed 8-CPA consumes relatively less power. In addition, the cascade LO topology of a delay-locked loop (DLL) synthesizer and an FM is proposed to perform the required stringent RMS jitter requirement beyond 5G+ wireless communication.
This article is organized as follows. In Section II, the topology of the proposed 8-CPA TX is introduced and its core circuitries are explained. Section III shows the chip fabrication and measurement results. In addition, a brief analysis of the test results is described in the last section of Section III. A summary and comparative analysis of the proposed modulator, along with recently published papers, are provided in Section IV.
II. Topology
As shown in Fig. 1, the proposed TX is divided into three subsidiary blocks (DLL, FM, and 8-CPA), which are highlighted in blue, red, and yellow, respectively. The DLL components are a digital differential-to-single (D2S) buffer, a phase frequency detector (PFD), a charge pump (CP), a loop filter (LF), a voltage-controlled delay line (VCDL), a two-single-to-differential complementary converter (2-S2DC), and an inverter (IHPL) of a half-period lock. An external microelectromechanical (MEMS) oscillator (SiT9501) differential outputs are converted to VMS through the D2S, and its output drives the PFD and the first delay unit (DU) in the VCDL. The phase difference between VMS and Vdel is manipulated by the PFD + CP, which adjusts VCT to control the delay of all the DUs simultaneously. When the phases of VMS and Vdel are locked, Vdel is delayed by Tref/2 from the rising edge of VMS due to the half-period lock, where Tref (= 1/fref) is the period of VMS. Therefore, each DU’s delay (TD) is uniformly equal to Tref/256. D1 and D2 are transformed to P0, N0, Pϕ, and Nϕ through 2-S2DC. An S2DC comprises two XORs—the top XOR input is connected to a ground, and the other XOR input is connected to a power supply. Therefore, the top XOR output would be identical to the input, but the bottom XOR output would be complementary.
The proposed 8-channel phased array transmitter block diagram.
The two outputs of 2-S2DC—(P0 and N0) and (Pϕ and Nϕ)—separately drive the chain of a harmonic generator (HG) and a buffer (BUF). The phase difference between P0 and Pϕ is π/128. Each chain consists of a harmonic generator1 (HG1), a buffer1 (BUF1), and an automatic constant amplitude control loop (ACACL). The HG and BUF output loads are identical parallels of an inductor (LS) and a capacitance bank (Cbank). The resonant frequency of the parallel of LS and Cbank is programmed to tune to 8 times the input fundamental frequency. Therefore, the intermediate frequency, fIF, is 1.25 GHz, and the phase difference between VIF0 and VIFθ is π/16. The proposed TX output frequency, fRF, is 10 GHz through the cascade chain of HG2 and BUF2 whose outputs are tuned to 8 times that of fIF. The phase difference between IRF and QRF is π/2. In other words, total phase multiplication equals the total frequency multiplication factor (TFMF = 64).
The 10 GHz I/Q signals (IRF and QRF) drive 8-CPA, which consists of 8 drive amplifiers (DAs) and 8 passive phase shifters (PPSs).
III. Circuit Design and PN Optimization
1. PFD + CP
Fig. 2 shows the PFD + CP schematics. A true single-phase clocking-based PFD (highlighted in blue) is implemented to operate high-frequency phase synchronization. It is optimized by following the PN optimization design procedure described in [12], leading to an on-time (TL) of 40 ps confirmed by simulation when 156.25 MHz input signals are locked.
Phase frequency detector and charge pump schematics.
To degenerate the current noises (
As explained in [13], Rdp and Rdn should be large enough to guarantee degeneration benefit. The proposed PFD + CP phase noise simulation is shown in Fig. 3. The PN floor is −144 dBc/Hz, and the PN at 1 kHz offset is −136 dBc/Hz.
PFD + CP phase noise simulation.
2. Delay Unit
The presented VCDL is a cascade chain of 128 DU cells. Each DU drives an identical DU’s input, but the last DU output is fed to the inverter for a half-period lock. Fig. 4 shows the DU schematic for the first 127 DUs. It consists of two delay unit inverters (IDUs), two varactors (Vars), and two 3-bit Cbanks. The DUout drives the multiplexer through the inverter buffer (IB). Adding a dummy buffer inverter (IB) at the DUX node creates the same capacitive load for the DUX and DUout nodes. In addition, another dummy inverter (IH) is applied to both the DUX and DUout nodes, where IH is the last DU load inverter. The last DU is almost identical to the first 127 DUs, but IH is replaced at the DUout node with IDU. Consequently, every output node of IDU in the chain of 128 DUs has the same capacitive load so that all the delays of IDUs are identical. Furthermore, the rising and falling delays of every DU are the same. The reason for the 3-bit Cbank is to reduce the DU gain, KDL, to make the DU less sensitive to the power supply and delay line noises, as well as to minimize the DU PN. Fig. 5 shows the 1st and 2nd DU PN simulations.
Delay unit (DU) schematic.
Phase noise simulations on DU1 and DU2.
The delay from DUin to DUout, DT, can be varied by adjusting the capacitance of Var, which is inversely proportional to the VCT magnitude. Fig. 6(a) shows the simulated DT versus delayed VCT when two extreme process/temperature variations of FF/−20°C and SS/100 °C are applied. The delay curves of FF/−20 °C (blue) and SS/100 °C (red) should be overlapped to overcome the variations of the ±3σ process and the −20 °C–100 °C temperature range. The overlapped delay must include Tref/256 to lock the DLL, which can be estimated as 25 ps when fMS is 156.25 MHz. The VCT node would converge to either 1.2 V or 0.9 V for both the FF/−20 °C/’111’ Cbank state and the SS/100 °C/’000’ Cbank state, respectively. Fig. 6(b) shows the simulated DT versus VCT when the supply voltage varies from 1.08 to 1.32 at TT/27 °C. Since the three curves do not overlap with one another, the VCDL power supply needs to be regulated as 1.2 V by a low-dropout regulator.
DU delay simulation (DT): (a) SS/100°C, FF/−20°C and (b) TT/27°C/supply voltage (1.08 V, 1.2 V, and 1.32V).
3. Frequency Multiplier
A tuned frequency multiplier (TFM) is generally composed of a HG, a band pass filter (BPF), and a BUF. An HG is nothing but an overdriven amplifier that produces a saturated output current. This saturated current is similar to the pulse waveform, which generates weak high-order harmonics compared to the fundamental tone. A desired high-order harmonic is reserved by a simple BPF. An additional amplifier is used as a BUF to further suppress unwanted harmonics. A TFM is the simplest frequency multiplier topology, but it suffers from a high level of undesired harmonics.
Recently, a new TFM topology has been introduced and successfully proven to significantly improve the harmonic rejection ratio (HRR) [13–15]. Its topology is the modified structure of a Gilbert cell double-balanced mixer. In this paper, the same TFM topology is used to tune the 8th harmonic of the input fundamental frequency. Fig. 7 shows the presented HG and BUF schematics. All the transistors (M1–M6) can be fully turned on and off by applying enough amplitude of (HGIP−HGIN). By adjusting CG, M1, and M3 sizes appropriately, a delay (TD) between HGIP and BTP can be generated. Fig. 8 shows the ideal voltage waveforms of HGIP, HGIN, BTP, and BTN. The corresponding ideal current waveforms (IM1–IM6, IHGN, IHGP, and IHGP–IHGN) are also shown. The M3 current (IM3) flows only when both HGIP and BTP are in a high state (‘1’). Because IM1 is always equal to the sum of IM3 and IM4, the high-state pulse width of IM4 is TD but that of IM3 is (TIN/2 – TD). Similarly, IM5 and IM6 can be generated by applying the complementary pulses (HGIN and BTN) of HGIP and BTP. The fundamental frequency of IM3–IM6 is fIN (= 1/TIN), but their summation (IHGP and IHGN) fundamental frequency is 2 × fIN. Therefore, the (IHGP–IHGN) pulse would provide strong evennumbered current harmonics.
HG and BUF schematics.
HG and BUF ideal timing diagrams.
When TIN is 6.4 ns, the period of (IHGP–IHGN) would be 3.2 ns. Fig. 9(a) shows the 3.2-ns period pulse with 20-ps pulse width, 20-ps rising delay, and 20-ps falling delay. The power spectrum is shown in Fig. 9(b). The power difference between 0.3125 GHz (2 × 0.15625 GHz) and 1.25 GHz (8 × 0.15625 GHz) is only 0.13 dB, which means that the power is more significantly balanced and distributed over a 0.3–1.25 GHz band compared with a 50% duty cycle pulse. Therefore, the proposed HG would provide a better HRR at the 8th harmonic.
Ideal (IHGP−IHGN): (a) pulse and (b) spectrum.
Since the proposed HG differential output voltage is simply the product of (IHGP–IHGN) and the parallel LS–Cbank load (Fig. 7), the unwanted harmonics of (IHGP–IHGN) around the resonant frequency are suppressed.
Fig. 10(a) shows the simplified HG output load, assuming a 1-bit Cbank. The capacitance (CPS) between HGOP and HGON (Fig. 7) is the summation of the fixed parasitic capacitances due to M3–M6 and the following BUF. RLS is the series parasitic resistance of LS. When MS is turned on, the turn-on resistance, RCS, is produced, as shown in Fig. 10(b). The series of LS and RLS can be transformed into the parallels of LP and RLP as
(a) Simplified HG output load, (b) HG output load when MS is turned on, and (c) parallel transform from the series of LS–RLS and CS–RCS to the parallel LP–CTP–RP.
where
where
where ω0 is the resonant frequency. When CTP is increased but LP is decreased, keeping ω0 constant, QP is improved if RP remains constant. However, increasing CTP leads to decreased QC, reducing RCP according to (3). Consequently, RP is decreased, which offsets the QP improvement by increasing CTP in (4).
To maintain a constant RP, a negative-gm differential pair (Q-Enhancer) is added at the HG output, as highlighted in yellow in Fig. 7. The positive feedback pair produces a negative resistance,
where K=2/gmRP which should be bigger than 1 to prevent it from oscillation. By adjusting K, REQ can remain the wanted constant value, even though RP is varied due to CP change. As a result, QP is increased to improve HRR.
Further suppression of undesired harmonics can be accomplished by the BUF following HG. The proposed BUF is the LS–Cbank tuned cascode differential amplifier. A negative-gm pair is also connected to the BUF output, but it plays the core role of the ACACL. The BUF differential output (VBP–VBN) is detected by a peak detector (Fig. 7). If the peak magnitude (VPK) is bigger than VR, the negative-gm pair current is reduced to make its gm lower. Increasing K leads to a decrease in REQ. Therefore, the BUF output decreases. In contrast, the BUF output amplitude increases when VPK is lower than VR. The negative-gm pair current varies until VPK converges with VR. As shown in [13, 14], the constant BUF output amplitude provides the best HRR performance for the following FM. The same cascade topology as the presented HG and BUF is used for both RF and mm-wave FMs. The only difference is that an active inductor is used for RMFM, but a passive inductor is used for mm-FM. The FM HRR performance is optimized by following the design procedure described in [13].
4. QRF and IRF PN Analysis
The proposed DLL’s critical PN sources are shown in Fig. 11, where θref is the spectral density (PNSD) of the reference clock. Also, θPC and θDL are the simulated PNSDs of the PFD + CP and the VCDL, respectively. ICP is the CP current. The DLL output PNSD, θdel, can be derived as
Phase noise sources of the proposed synthesizer.
where
Then, the proposed output PN can be
While the noise transfer function (NTF) of the θPC, HL(S), is a low-pass filter and the NTF of θDL, HH(S), is a high-pass filter, there is no filter effect on θref. Therefore, θref is multiplied by TFMF and directly transferred to the synthesizer output.
As shown in Figs. 3 and 5, the DU phase noise is much smaller than that of the PFD + CP. Therefore, the integrated RMS jitter improves with the reduction of the DLL bandwidth is reduced. In addition, the CP phase noise at the 1 kHz offset is −136 dBc/Hz, much less than that of SiT9501, the phase noise of which is −119 dBc/Hz at the 1 kHz offset. Therefore, the DLL phase noise is almost equal to SiT9501’s phase noise if the 3-dB DLL bandwidth is less than 1 kHz. To set the 1 kHz 3 dB DLL bandwidth, ICP = 20 μA, delay line gain KDL = 1.5 radian/V, and loop filter capacitance CL = 10 pF.
5. Phase Shifter Modulator and Drive Amplifier
The proposed PSM block diagram is shown in Fig. 12(a). The sign control bits, DSi and DSq, decide either IIN or IIP and either QIN or QIP as each path presents a passive amplitude modulator (PAM) input, respectively. Its component, the proposed PAM schematic, is also shown in Fig. 12(b). The PAM output can be directly modulated by programming 6-bit data (‘D6D5D4D3D2D1’). Two identical Cbanks are connected in a ladder structure. The digital control bits, Dks, are applied to the top Cbank but the complement digital control bits,
(a) The proposed PSM block diagram and (b) the proposed PAM.
where
and
Cdk is the total parasitic capacitance between the drain of Mk and the ground when Mk is turned off. The sizes of Mk and Ck are binary-weighted as 2 × Mk = Mk+1 and Ck+1 = 2 × Ck, which leads
If adjusting C1 is equal to
When the states are ‘000000’, ‘000001’, ‘111110’, and ‘111111’, the numerators of (13) are
The vector modulation of applying the I/Q AMs results in constellation points (64 × 64) in the first quadrant, as shown in Fig. 13. Among them, the closest to the target I/Q sets are highlighted with blue circles in Table 1. The maximum phase and amplitude errors are ±0.909° and 0.00775. The phase shifts in the last three quadrants are covered by varying DSi and DSq sign bits, as shown in Fig. 12(a).
The first quadrant constellation points of 64 × 64.
The I/Q sets of 5.625º phase resolution phase shift
The proposed PAM can provide linear amplitude modulation digitally because capacitive divider output does not depend on frequency but rather on capacitor ratio. It is efficient to implement a wide frequency band. In addition, the capacitive ladder structure is less sensitive to PVT variations (±3σ process, ±10% power supply voltage, and temperature ranging from −20°C to 100°C) compared with other counterpart topologies.
The common source with the source follower load is applied as a DA (Fig. 14(a)). Fig. 14(b) shows the simulation plot of the DA output (VOUT) versus the input (VIN). The DA power gain is 0 dB, and the output 1-dB compression point (OP1dB) is 14.6 dBm when it consumes 1 mW.
(a) Drive amplifier schematic diagram and (b) output 1-dB compression point (OP1dB) simulation.
IV. Chip Fabrication and Test
The proposed TX is fabricated on 65-nm CMOS technology with a die size of 2 mm2 including I/O pads, as shown in Fig. 15. Many pads for the power supply and ground are used to isolate each functional block. The pads of VDDCP3 and GNDCP3 are for 2.5 V devices, and the pads of VDDCP1 and GNDCP1 are for 1.2 V devices in the PFD + CP. Separate guard rings (GRs) for GNDCP3 (GRCP3) and GNDCP1 (GRCP1) are drawn to isolate their substrates. VCDL’s jitter performance is sensitive to power supply noise. Therefore, VCDL needs a separate power supply. It also requires GR (GRCP3) to prevent interference from other digital blocks by connecting GRCP3 to GNDCP3, 100-μm apart.
Die micrograph of the proposed modulator.
A separate power supply and ground for each chain of phase shifter and DA is essential to isolating each other. Otherwise, owing to mutual interference, it is difficult to beamform at an antenna array. Each DA’s ground pad is close to the output to ensure efficiency in implementing GR, even though the power supply connection is long.
The minimum width of the GRs mentioned above is 30 μm to guarantee more than 42 dB of substrate isolation within 100 μm [16].
The chip test setup block diagram is shown in Fig. 16. The proposed TX outputs (TX1–TX8) are measured by a spectrum analyzer (Keysight E4446A) and a network analyzer (Keysight E8361A) applying a Keysight E3631A as the power supply for the test PCB.
Test setup block diagram.
A laptop programs the device under test through an SPI for the best performance. Three sample chips (Chip#1–Chip#3) are mounted on a PCB using the chip-on-board technology and tested by applying a differential MEMS oscillator (SiT9501) as a reference clock. The DA outputs are placed as close to the PCB pad as possible so that the parasitic inductor would be the smallest. The estimated bonding wire inductor is about 0.35–0.4 nH. The TX1–TX8 outputs are individually matched to 50 Ω with off-chip passive components. The detail-matching circuits are omitted for simplicity. Fig. 17 shows the TX1–TX8 S22 measurements of Chip#1. The worst S22 is less than −10 dB for the target measurement frequency band of 9.5–11.5 GHz.
S22 measurements of TX1–TX8.
The measured average power consumption of the I/Q-IFFM and the I/Q-RFFM are 8.1 mW and 5.2 mW, respectively. The reason for more power consumption on the I/Q-IFFM is that a 2.5 V power supply is used to secure enough headroom to overcome the voltage drop due to the active inductor load. A 1.2 V power supply is applied to the I/Q-RFFM. The DLL consumes 4.5 mW. Each DA burns 1 mW, leading the total power consumption of the 8-CPA to be 8 mW (8 × 1 mW). The proposed TX’s power consumption is 27.8 mW, including the power consumptions of a reference current bias and two ACACLs.
As shown in Fig. 18, the measured phase noise degradations between the input and output of the 64-times FM are about 36.23 dB at 10 GHz output frequencies. These results are very close to the mathematical phase noise deterioration (36.124 dB = 20log(64)). In other words, the proposed cascode of the DLL and FMs is proven to add negligible phase noise to the input signal. The integrated RMS jitter from 12 kHz to 20 MHz is 72 fs.
Phase noise degradation at 10 GHz.
The measured output spectrum on TX1 is shown in Fig. 19(a) when fRF is 10 GHz. The worst HRR happens at the 2fref offset from 10 GHz but is bigger than 60 dBc. There are notable fundamental frequency-related spurs, even though great effort has been made to study symmetric topology and its symmetric layout. Therefore, the nearest adjacent tone around the wanted harmonic is the fundamental tone (fref). Fortunately, its HRR is greater than 65 dBc. Fig. 19(b) shows a summary of the worst HRRs on TX1–TX8.
(a) TX1 spectrum. (b) TX1–TX8 worst harmonic rejection ratios.
Fig. 20 shows the measured phase state plots of the 5.625° phase shift step over the 0°–360° range. Each constellation plot is the individual crowd measurement result of 100 data programmed by the SPI.
Phase shift for 64 states.
V. Summary and Conclusion
This paper presents an 8-CPA transmitter for a 5G+ application. It consists of a DLL, an FM, and an 8-CPA. DLL is used to improve PN performance at low frequencies. FM increases the frequency 64 times, and PN is proportional to the multiple ratios of FM. It has been proven that noise due to FM is similar to mathematical phase noise. A high-resolution phase shift is possible through PPS, which consumes no power.
Table 2 shows the performance comparison of other phase shifters [17–19]. Vector modulator-based active phase shifter, one of the most popular active phase shifter, consumes high DC power. In contrast, PPS burns no DC power. The resolutions of [18] and [19] provide the best performance. The proposed phase shifter achieves an outstanding overall performance compared with other phase shifters.
Performance summary and comparison
Notes
This work was supported by the Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MSIT) (No. 2020-0-00216, Development of mmWave data conversion free phased-array Tx based on 6PMP). The Eda tool was supported by the IC Design Education Center (IDEC), Korea.
References
Biography
Kyu-Hyun Nam, https://orcid.org/0000-0003-1584-3150 received B.S., M.S., and Ph.D. degrees in electrical engineering from Kookmin University, Seoul, South Korea, in 2012, 2014, and 2022, respectively. He is currently a post-doctoral research fellow in electrical engineering at Kookmin University, Seoul, South Korea. His research interests include the RF/microwave/mm-wave wireless communication systems and RF, analog, and mixed-mode circuit designs.
Nam-Pyo Hong, https://orcid.org/0000-0001-5493-6435 received B.S., M.S., and Ph.D. degrees from the School of Electrical Engineering, Chung-Ang University, Seoul, South Korea, in 2007, 2009, and 2015, respectively. From 2015 to 2018, he was a post-doctoral research fellow in electrical engineering at Kookmin University, Seoul, South Korea. He was a senior researcher with the ICT Device and Packing Research Center at Korea Electronics Technology Institute (KETI) from 2019 to 2020. He is currently a research professor at Kookmin University. His research interests include RF, analog, and mixedmode circuit designs for mobile communication.
Junseok Park, https://orcid.org/0000-0002-4223-7706 received B.S., M.S., and Ph.D. degrees from Kookmin University, Seoul, Korea, in 1991, 1993, and 1996, respectively, all in electronics engineering. In 1997, he was a senior researcher with the Department of Electrical Engineering, University of California at Los Angeles (UCLA). From 1998 to 2003, he was an assistant professor at the Information Technology Engineering Division at Soonchunhyang University, Asan, Korea. He is currently a professor at the Department of Electrical Engineering at Kookmin University. In 2009, he was invited as an associate professor with the expert research group of The California Institute of Technology (Caltech), where he contributed to many low-noise/high-speed system/platform research activities. From 2013 to 2019, he was a member of the key expert group for IoT convergence (Brain Korea 21 program), where he collaborated with many core design groups for wireless power transfer and energy charger systems and platforms. During the same period, he was also a leading partner of the National Engineering and Science R&D group (Minister of Land, Infrastructure, and Transport), developing the stationary power platform for electrical vehicles. From 2015 to 2017, he was a committee member of the smart sensor network R&D group for safety control. From 2017 to 2020, he was one of the R&D committee groups of the Korea Energy Agency for the development of the ESS-based uniform network. Recently, he has been a leader of the future 5G convergence and computing technology program of the Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MSIT) for developing the high-performance phased array system. His research interests include the RF/microwave/mm-wave/THz and SoC and MMIC; the numeric methodology for integrated metamaterial applications; EBG and DGS; solid-state ground configuration and optimization; low-noise phased array for the military/automotive radar systems; and uniform smart RF signal/power circuit driven by machine learning.