Modeling and Manufacturing AAO-Based Micropatterned Chip Inductors for GHz Applications

Article information

J. Electromagn. Eng. Sci. 2025;25(1):92-99

Publication date (electronic) : 2024 December 19

doi : https://doi.org/10.26866/jees.2025.1.r.260

Rachida Lamouri^1,2, Dongyoon Kim¹, Baekil Nam¹, Taehwan Song³, Seungho Park³, Wanho Kim⁴, Ki Hyeon Kim^1,

¹Department of Physics, Yeungnam University, Gyeongsan, Korea

²Institute of Applied Physics, Mohammed VI Polytechnic University, Benguerir, Morocco

³R&D Center, Point Engineering Inc., Hwaseong, Korea

⁴Smart Lighting Research Center, Korea Photonics Technology Institute, Gwangju, Korea

^*Corresponding Author: Ki Hyeon Kim (email: kee1@ynu.ac.kr)

Rachida Lamouri and Dongyoon Kim contributed equally to this work.

Received 2024 March 27; Revised 2024 May 20; Accepted 2024 June 11.

Abstract

I. Introduction

Over the past decades, international connectivity through wireless communication systems has attracted the attention of both research groups and industrial technology providers [1–6]. To achieve the desired high-speed connectivity, optimizing the performance of radio-frequency devices, with a focus on the possibility of using them at frequencies above 10 GHz [7, 8], has been considered significant.

Along with technological development in wireless systems, miniaturized inductors characterized by high performance at high frequencies have become essential to ensure the safety functions of all integrated circuit components, such as oscillators, filters, and impedance matching networks [9, 10]. This has paved the way for extensive research and investigations into the electrical properties of inductors, such as Q-factor, inductance, self-resonance frequency (SRF), and heat dissipation, which define their prospective applications [11].

Surface mount inductors are classified into thin film, multi-layer, and wire-wound inductors. Notably, compared to multi-layer and thin-film inductor structures, wire-wound inductors present significant advantages, such as low DC resistance and low parasitic capacitance between coils, which provide high Q-factor and SRF at the high-frequency range [12–15].

Moreover, based on the desired application of the wire-wound chip inductor, the wire can be wounded to nonmagnetic ceramics, air, or ferrites [11]. In particular, alumina has been widely used as a high-frequency inductor substrate and package owing to its insulating properties, mechanical strength, and outstanding thermal and chemical stability, which helps accomplish the best performance in a miniaturized package. However, its relatively high dielectric constant causes a delay in signal propagation, thus restricting its use in some applications [16, 17].

Existing manufacturing processes for wire-wound chip inductors usually involve winding an external mechanical wire around the core material [15, 18]. However, despite the good performance of externally wound chip inductors, it entails a difficult manufacturing process that necessitates very expensive technologies for fabricating a scale-up production process with featuring a miniaturized size.

In this work, we demonstrate the design and fabrication of a micropatterned internal wire-wound chip inductor featuring 4.5 turns by implementing a photolithography process that involves using an anodic aluminum oxide (AAO) 6-inch wafer with a thickness of 100 μm. Furthermore, different coil widths were simulated to optimize the performance of the micropatterned inductor before proceeding with the manufacturing process using photolithography.

II. Design and Simulation

As presented in Fig. 1(a) and 1(b), the proposed 3D model of the wire-wound chip inductor comprises an internal winding of the Cu coil situated at an optimized distance from the edge of the alumina-based substrate (B = 50 μm). Detailed model dimensions are listed in Table 1.

Fig. 1

(a, b) The simulation model, (c) 3D schematic, and (d) equivalent circuit of the simulated 4.5-turn wire inductor.

Table 1

Specifications of the designed wire-wound chip inductor

The dimensions of the substrate were chosen as 1.5 mm × 0.7 mm × 1.0 mm for the packaging dimension of 2010 size (2.0- mm length and 1.0-mm width) with 4.5 turns. Three different coil widths (20 μm, 30 μm, and 40 μm) were simulated using the ANSYS electronics package, with the gap between the coils kept constant (Gap = 40 μm) with the different coil widths. A three-dimensional (3D) schematic diagram and the equivalent circuit of the proposed inductors are shown in Fig. 1(c) and 1(d).

Electromagnetic simulation at a high frequency was performed using ANSYS High-Frequency Structure Simulator (HFSS) software. The radiation boundaries were defined using an air box with a larger volume than the inductor size, representing infinite space. Lumped ports were employed to supply the reference impedance (50 Ω) from the S-matrix and the excitation source.

The performance of the designed wire-wound chip inductor was analyzed in terms of its inductance, Q-factor, and resistance. In particular, the scattering parameters (S) and impedance matrix (Z) obtained from the HFSS estimations were used to calculate the inductance (L), Q-factor (Q), and resistance (R) using the following formulas [19, 20]:

The inductance, magnetic flux distribution, impedance, Q-factor, and distributed capacitance were simulated as functions of the frequency for the three coil widths of 20 μm, 30 μm, and 40 μm, as shown in Fig. 2. Fig. 2(a) illustrates that the SRF increased from 12.4 GHz to 15.3 GHz with an increase in the coil width from 20 μm to 40 μm. However, the inductance value at 250 MHz decreased from 7.49 nH for a coil width of 20 μm to 6.70 nH for 30 μm and 6.09 nH for 40 μm. Furthermore, since the magnetic flux distribution in an inductor is closely related to its inductance, Fig. 2(b) presents a cross-sectional view of the magnetic flux distribution along the xz- and yz-planes at 250 MHz for each model, exhibiting a homogenous and uniform distribution of magnetic flux for all three models. However, the maximum value of the total magnetic flux density decreased with an increase in the coil width, as expected with regard to the obtained decrease in inductance.

Fig. 2

Simulation results of the chip inductor: (a) inductance and impedance as functions of the frequency, (b) H-field distribution for different coil widths, (c) Q-factor as a function of the frequency, and (d) distributed capacitance as a function of the frequency.

The Q-factor values for the three coil widths exhibited an increase with an increase in frequency, as depicted in Fig. 2(c). We also found that by compromising a bit of the inductance, the Q-factor at 250 MHz improved from 25.1 for 20 μm to 32.0 for 40 μm. The maximum values of the Q-factor were around 80.5 at 5.0 GHz, 93.5 at 5.8 GHz, and 105.0 at 6.3 GHz for coil widths of 20 μm, 30 μm, and 40 μm, respectively.

At high frequencies, impedance is an important feature to take into consideration for further practical use of the inductor. The impedance, calculated as a function of the frequency using ANSYS HFSS software, with regard to the inductance and Q values is presented in Fig. 2(a) and 2(c). At 250 MHz, the impedance of the simulated inductor decreased from 0.47 Ω for 20 μm to 0.30 Ω for 40 μm—consistent with the decrease in inductance and increase in Q-factor. Moreover, the impedance value increased with frequency, which can mainly be attributed to high-frequency phenomena, such as proximity and skin effects [21]. As for the distributed capacitance between coils, a very small negative capacitance was observed for the pF order below the SRF, while a positive capacitance was found for the pF order above the SRF, as shown in Fig. 2(d). Consistent with previously reported results [22], it was found that a small distributed capacitance could not significantly affect the SRF in the proposed inductor model.

III. Manufacturing and Measurements

Owing to its moderate parameters, as obtained from the HFSS simulation, representative model B in Table 1 was chosen as the micropattern wire-wound chip inductor for manufacturing. This model was fabricated by photolithography process on an AAO 6-inch wafer of anodic, as described in Fig. 3(a).

Fig. 3

(a) Cross-sectional illustration of the photolithography process and the fabricated chip inductors patterned on a 6-inch AAO wafer. (b) The inductor packaging process, with real images of the wire-wound chip inductor before packaging.

Notably, AAO was chosen over an alumina substrate because of the decrease in its dielectric constant caused by porous air holes, which reduces the parasitic capacitance of a substrate [23, 24]. Unlike existing commercial inductors in which the wire is wounded outside the substrate, the Cu coil of the proposed inductor was connected into the AAO substrate through a via-hole between the top and bottom coils, through a via-hole. To fabricate the chip inductors, one side of AAO substrate bonded to the carrier wafer after the seed layer for an electroplating process at the bottom of the AAO platform. And then the other plane of AAO wafer proceed in the same process. Next, the AAO substrate in the via-hole area was perforated by using photoresist (PR) pattern. After AAO etching to allow the via hole growth, the metal was plated from the bottom seed layer of AAO substrate. Subsequently, the AAO substrate was partially covered with a PR layer to create coil rods within the AAO body. Ultimately, the AAO comprised spaces corresponding to the through via in the body, which were filled with a monolithic Cu layer at the bottom of the body through an electroplating process.

To planarize the pattern on the AAO, the over plated coil rods of Cu was removed by implementing a chemical mechanical polishing (CMP) process. A second seed layer was coated onto the AAO surface, after which open areas were prepared on the AAO body using photoreactive material to establish a connection of the Cu patterns with the coil rods. Next, the AAO was separated from the carrier substrate, after which the platform underwent a second bonding process at the opposite plane, from the bottom to the top. Another Cu pattern connected to the coil rods at the exposed bottom surface was separated from the carrier wafer by photolithography and electroplating processes, following which the photoreactive layer was removed. Notably, before the CMP process, the via-holes were first patterned, etched, and then planarized. A lithography process was conducted for the top coil of the inductor, after which the process was reversed for the bottom coil. Subsequently, the fabricated inductors were packaged by carrying out the process shown in Fig. 3(b), which consists of three major steps: die bonding, molding, and dicing.

The test fixture using microstrip line based on the IEC 62024 standard was employed to measure the properties of the proposed micropatterned inductor after TRL (thru-reflect-line) calibration, as shown in Fig. 4(d). The network analyzer (Rohde & Schwarz ZNB40 and Keysight N5222B) was used to measure the S-parameters, which were later converted to calculate the impedance matrix (Z). The measured inductance, Q-factor, impedance, and distributed capacitance for the inductor with 30 μm-coil width are presented as functions of the frequency in Fig. 4(a)–4(c), respectively. The inductance, Q-value, and SRF of the micropatterned wire-wound inductor were found to be around 5.9 nH at 250 MHz, 18.1 at 250 MHz (Q_max = 66.7 at 2.9 GHz), and 12 GHz, respectively, showing lower values than the simulated results (6.7 nH at 250 MHz, 30 at 250 MHz, and 14 GHz, respectively). Furthermore, the distributed capacitance of the patterned chip inductor displayed negative values below the SRF, which transitioned into positive values beyond the SRF. This behavior aligns closely with that of the simulated inductor, as depicted in Fig. 4(c).

Fig. 4

The measured (a) inductance, (b) Q-factor, (c) distributed capacitance as functions of the frequency for the fabricated chip inductor, and (d) the test fixture and TRL calibration kit.

Notably, Le et al. [25] fabricated 3D air-core inductors, embedding them in a silicon substrate with 20 and 25 turns, to attain higher inductance values, ranging from 34.2 to 44.6 nH, compared to the values obtained for the inductor proposed in this study, primarily due to the substrate used and the number of turns. However, Le et al. [25] attained a low Q factor of up to 13. Moreover, the inductance and Q-factor values obtained for the manufactured inductor were significantly smaller than those achieved by the designed 30 μm-width Cu coil. This difference between the simulated and measured results can be attributed to the different defects that occur during the manufacturing process compared to the perfect conditions of a simulation, in addition to the higher resistance value of electroplated Cu compared to pure Cu wire.

IV. Conclusion

In this study, we designed and manufactured a micropatterned wire-wound chip inductor for high-frequency applications. Before proceeding with the lithography process to micropattern the inductor using a 6-inch wafer of AAO as substrate, a simulation analysis was performed using the ANSYS HFSS package. Different model parameters were considered to optimize the performance of the inductor in terms of inductance, Q-factor, and AC resistance. Our results showed moderate performance of the micropatterned inductor with a coil width of 30 μm. These results are expected to be applicable for actual high-frequency circuits using the proposed micropatterned wire-wound inductors.

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