Survey on Advances in Broadband Signal Generation and Processing of ASIC Semiconductors for Defense Satellites
Article information
Abstract
To replace the field-programmable gate array semiconductors used in the defense satellite industry, we conducted a technical investigation of application-specific integrated circuit (ASIC) semiconductors. The analysis results show that ASIC semiconductors have the heat dissipation, reliability, and radiation resistance capabilities required in a space environment and excellent performance indicators related to the resolution of synthetic aperture radar payloads, such as operating frequency. Research and development of mission-customized ASIC semiconductors that fit the requirements for NSP(new-space paradigm) should be preceded to expanse bases of the space industry, national security capabilities for next-generation space deveolpment also to secure competitiveness of technology and domestic supply chain as space parts itselfs.
I. Introduction
Prior to the 1990s, analog voltage-controlled oscillators were mainly used for signal generation and module processing, which are the core components of synthetic aperture radar (SAR) sensors for satellites. However, the instability of the signal generated by the transmitter has led to consistent poor performance of SAR sensors.
Since the 1990s, the development of digital field-programmable gate arrays (FPGAs) has been developed mainly as a way to improve this situation. Current research on the design and production of application-specific integrated circuits (ASICs), in terms of performance, power efficiency, and integration, has been more active than research on FPGAs within the space industry in advanced countries [1–3].
ASICs are key components used to generate broadband radar chirp signals, process high-performance broadband signals, and control operations. Thus, it is necessary to secure technology and design products for obtaining ultra-high resolution images of SAR sensors in the future. Once research and development of ASICs, which are currently being introduced by Thales Alenia Space Italy, is completed, they are expected to become both an independent space technology and a space powerhouse for satellite core components.
II. Investigation and Analysis of ASICs
1. Main Characteristics
ASICs, which are mounted on SAR sensors, are key components used to generate and process broadband radar information signals for obtaining ultra-high resolution image information. The shape, function, and specifications of ASICs are shown in Table 1.
Functions and specifications
2. Technology Trends
2.1 Domestic markets
Korea’s global market share for semiconductors is 21%; however, its global market share for system semiconductors such as ASICs has stagnated at 3.2%. This is especially evident for its fabless share of 1% in Korea, which is significantly lower than the fabless shares of 17% and 15% in Taiwan and China, respectively. Korea’s system semiconductor technology level is comparable to that in the United States, Europe, and Japan but is higher than that in China, rising slightly from 77.3% in 2013 to 80.8% in 2022.
Future investment in system semiconductors such as ASICs is expected to expand due to strategic changes and policy support from major companies. Samsung Electronics plans to invest 133 trillion Korean won by 2030 to expand system semiconductor research and development production facilities and will support small amounts of production by supporting design assets and easing consignment production standards to strengthen product competitiveness and shorten development periods [4].
2.2 Foreign markets
McKinsey, a global consulting firm, predicts that the semiconductor market, which will be applied to various fields such as learning, natural language processing, and reasoning, will grow 18% yearly, accounting for 20% of the total semiconductor demand by 2025.
In addition, Deloitte calculated semiconductor sales in 2016 with approximately 100,000 units, for which the graphic processing unit (GPU) accounted for most of them. However, when analyzing semiconductor sales in 2018, it diversified from approximately 800,000 units to 500,000 GPUs, 200,000 FPGAs, and 100,000 ASICs. This diversification raised expectations that FPGAs and ASICs would hinder GPU dominance, and ASICs are expected to account for the largest portion of all semiconductors by 2025 [5]. The main features are shown in Fig. 1.
Deep learning chipset unit shipments by type, world markets (2018–2025).
A market research firm predicts that the semiconductor market will grow from $1.6 billion in 2017 to $66.3 billion by 2025. In terms of sales, the ASIC market is expected to be dominant by 2025, followed by the GPU and central processing unit (CPU) markets. Approximately 97% of data centers are GPU-based for current learning purposes, but by 2025, the share of GPU-based data centers is expected to plunge to 40%, and ASICs will account for approximately 50% of these centers and divide GPU and its market.
In the inference data center, ASICs are expected to continue to reduce the proportion of CPUs that account for 75% of the existing CPUs, resulting in 50% CPUs and 40% ASICs by 2025. Similar developments are expected to continue in the computing stage. Although ASICs and CPUs are currently dividing the market for learning purposes, it is expected that ASICs will become a trend by securing approximately 70% of ASICs by 2025, and FPGAs will account for 20% of the new CPUs, and CPUs will be completely eliminated.
3. Necessity of Development
In the process of developing domestic SAR payloads, the need for broadband signal generation and processing ASICs based on military, technical, and economic future scalability was confirmed.
3.1 Military aspect
To preemptively develop technologies for key components that significantly impact the SAR payload performance of military reconnaissance satellites, it is necessary to secure a space active device design, manufacture, test, and verification plan to alleviate the development difficulty according to the development cost/period of existing medium and large surveillance assets.
Standardized ASICs should also be applied to SAR-mounted equipment of subsequent military reconnaissance satellite systems or micro-satellite systems, thereby applying ASICs to advanced defense such as combat drones and drone technologies and preparing for future wars using small and light SAR payloads [6].
3.2 Technical aspect
To overcome the substantial technical barriers to the development of space ASICs and the technology gap with advanced countries, it is necessary to secure highly integrated ASICs and signal processing technology, radiation/thermal robust design technology, and high reliability satellite component manufacturing technology.
This will enable the cultivation of surveillance and reconnaissance capabilities through the timely provision of high-resolution images and contribute to the development of experts in the design, production, and testing of space-based ASICs and the core design of SAR control units, as well as the expansion of the technological base.
3.3 Economic aspect
To overcome the large technical barriers to space ASIC development and the technology gap with advanced countries, it is necessary to secure intensive ASIC and signal processing technology, radiation, and thermal robust design technology.
This enables the cultivation of surveillance and reconnaissance capabilities by the timely provision of high-resolution images and contributes to training experts in space ASICs design test, SAR control unit core design, and expanding the technology base.
4. Required Technology
4.1 Broadband radar signal generation
Broadband radar signal generation is an algorithm technology that generates waveforms with low clocks in parallel according to waveform variables in a space environment, where the use of high frequency is not feasible, and it cannot be generated using commercial direct digital synthesis (DDS) due to performance degradation of logic devices using high-speed clocks.
The DDS principle is designed by internalizing it into the FPGA with hardware description language, and DDS is driven in parallel to reduce each core operating frequency to the 1/N clock to generate a wideband waveform, as shown in Fig. 2.
Equilibrium frequency system concept.
4.2 Broadband waveform compensation
Broadband waveform compensation is a technology that automatically compensates for wideband waveform distortion according to temperature and the frequency to generate. Stable waveforms are achieved by measuring the distortion and implementing compensation tables.
Additionally, the DDS output was automatically compensated according to temperature/frequency. The main features are shown in Fig. 3.
Satellite frequency and amplitude compensation circuit applied to parallelized direct digital synthesizer.
4.3 Broadband radar signal processing
In space environments, efficient resource management and parallel signal processing are required to handle broadband signals without their being pushed given the performance degradation.
The technical content is to select unnecessary signals that are repeatedly input to broadband signal input and process broadband waveforms without delay within a given resource by processing them in parallel at high speeds for the remaining signals.
4.4 ASIC circuit design
ASIC circuit design is a technology that optimizes the frequency, power consumption, and timing characteristics of waveform generation. The FPGA includes many unnecessary logic cells to implement re-program characteristics [7]. The circuit design for ASICs and FPGAs is shown in Fig. 4.
Concept of ASIC and FPGA circuit design.
4.5 Foundry process conversion
To satisfy the performance required for very-large-scale integration (VLSI), it is necessary to analyze and optimize the performance at the fabric level to which the process is applied. Foundry process conversion technology performs place & routing and layout design on semiconductors and improves performance through circuit path optimization and space usage analysis [8].
4.6 Reliability design and validation
Reliability design and verification is a technology that analyzes the impact of temperature, voltage, and verifies the manufactured hardware. Quantitative analysis and verification of performance degradation are essential to secure highly reliable space-integrated circuits in harsh environments such as space.
Test bench technology for design and reliability design verification through analysis of integrated circuit performance according to temperature, voltage, and radiation effects should be secured.
4.7 Radiation
To evaluate the effects of total ionizing dose, it is necessary to verify the results of single-particle radiation environment simulations and single-particle tests and to perform a single-event effects test [9, 10].
4.8 Space environment
This process is conducted to test and verify robust performance by space environment simulation and to test the equipment design. Vacuum, ultraviolet, thermal cycle, and oxygen plasma environment simulation technology, as well as evaluation technology to detect changes in physical properties, are utilized. Details include launch environment tests that simulate vibrations generated during a satellite launch to ensure stable operation and quality of the environment exposed to space [11, 12].
4.9 Screening
This technology evaluates the reliability of the manufactured transistor in the space environment through screening mass-produced components and verifies their function, performance, and quality using environmental certification models or flight models.
5. Expectation Effectiveness
The development of ASICs for space is expected to have excellent effects in terms of technology/industry, economy, and exports. The development of small and light payloads can create new industries and create a virtuous cycle of industry by leading research and development investment to create new growth engines for space development.
Additionally, the development of ASICs can promote the participation of private companies in the aerospace industry in the manufacture of satellite parts centered on individual and low demand. Examples of this participation include expanding the satellite information service industry and competitiveness of secure technologies compared to advanced space industries.
After successful localization development, the applicability of the system above the module level can be reviewed to replace the core components of the SAR payload, which were necessary for importation, and to secure the export potential of the core components of the SAR payload. In addition, it is possible to increase the efficiency of the SAR system of various frequencies by expanding the waveform generator and digital receiver from the base band to other bands.
6. Performance Comparison (ASIC - FPGA)
6.1 High-resolution imaging
SAR-mounted equipment is continuously improving its resolution for accurate monitoring and reconnaissance of targets and in the case of current satellites. A chirp waveform generator with a broadband instantaneous bandwidth and a receiver structure to process it are required.
It is essential to improve broadband waveform generation technology to achieve high resolution of SAR-equipped equipment, which is related to the operating frequency of the signal generation module. ASICs are approximately three times better than FPGAs. The main features are shown in Table 2.
Maximum operating frequency comparison test results
To compare the maximum operating frequencies of FPGAs and ASICs, 21 functional blocks were set and tested. The test results confirmed that the maximum operating frequency of ASICs was more than 3.3 times better than that of FPGAs. In particular, there is a difference of approximately five times in the booth block, so when ASICs are utilized, the function is superior at a specific frequency.
6.2 Miniaturization/multiplexing
Satellite SARs are generally developing in the form of operating many small satellites. The Mini-SAR, developed by Sandia Laboratory in the United States, is small and lightweight with a total weight of 22.7 kg. The German satellite, SAR-Lupe, consists of five smaller satellites and operates as a satellite. FPGAs requires additional TR as it configures logic in a configurable logic block (CLB) manner, whereas ASIC constructs circuits based on modules when expressing logic.
6.3 Reliability/stability
It is necessary to develop high-quality products to ensure durability and maintain performance in space environments that are exposed to radiation for a long time to minimize power consumption for the stable operation of satellite SAR equipment.
In a vacuum universe, power consumption generally leads to heat generation. The ASIC consume approximately 10 times less power than the FPGA, so they it is suitable as a space device. The related features are shown in Table 3.
Power consumption comparison test results
Taking into account the space environment, 21 functional blocks were set up to confirm the power consumption of each FPGA and ASIC. The power consumption difference was approximately 30 times in the booth block and 25 times in the rsencoder block, and the power consumption of each ASIC was approximately 10 times lower on average than each FPGA. High reliability can be maintained if an ASIC is used in a space environment that is vulnerable to heat generation.
7. Research Results
The ASIC development process is shown in Fig. 5. First, the FPGA verified code is converted to ASIC code for simulation, and the verified code is synthesized into logic to create a netlist. The netlist is then verified before performing the back-end layout through dynamic timing simulation. If a problem with timing arises, register transfer level (RTL) code modification is performed to ensure that the requirements are met.
Development process of an ASIC.
The back-end process for ASICs includes floor-plan work to determine the location of memory, intellectual property (IP), and IO-pad, placement of each cell, clock tree synthesis (CTS), and net routing. The layout is determined through CTS and net routing, and the parameters are extracted and used for dynamic timing simulation, static timing analysis, and verification. Simultaneously, we prepare the package of the ASICs, set up the test environment, and perform functional testing and reliability checks on the ASICs.
Next, we need to convert the memory blocks used by the FPGA to the memory provided by the ASIC library and the logic IP used by a fast Fourier transform. We also need to create a simulation environment to verify that the code converted to the ASIC RTL performs the same functions as the FPGA code.
After this verification, preparation for logic synthesis is necessary. The inputs needed for logic synthesis are the ASIC-converted RTL and the tool commands for your design specification. In addition, functional and timing verification of the converted netlist after synthesis is performed to analyze whether the circuit was synthesized according to the design intent. The required inputs are the input test vectors used in the simulation, the synthesized netlist, and the standard delay format (SDF).
We perform the ASIC back-end process of placing the functional blocks into their actual physical form. The first step is floor planning, which involves organization of the functional blocks. The main contents include the size of the chipset, the placement of signals, and the placement of power and ground pads. The impact of signal and power on noise sources is analyzed. Once the rough layout of the functional blocks has been determined, the next step is ASIC IP placement, which is the detailed placement of the standard cell IP. The chipset area, power consumption, and thermal stability of the placement are the main considerations.
III. Conclusion
To develop an SAR sensor broadband signal for the generation and processing of ASICs used in military reconnaissance satellites, this study investigated related domestic and foreign technology trends, required technologies, and development requirements (functions and performance, test evaluation, etc.) in stages. Research and development of space-grade ASICs can be utilized in weapons systems and new industries, such as the space field, which requires radiation resistance, and the aircraft field, which requires high reliability, and can contribute to the development of the domestic industry by increasing the import substitution effect for core devices for space satellites.
In addition, it is believed that ASICs can serve as a new growth engine to further solidify the basic infrastructure of the domestic space satellite industry and secure future technologies by efficientizing functions and performance compared to existing FPGAs while ensuring system reliability and longevity.
References
Biography
Bo-Hyun Shim, https://orcid.org/0009-0001-8910-1961 received a B.S. from Korea Maritime and Ocean University, Department of Nano-Semiconductor Engineering, Busan, Korea, in 2011 and an M.S. from Gwangju Institute of Science and Technology, Department of New Materials Engineering in 2013. He is currently working as a senior researcher at KRIT, Jinju, Korea. His research interests include communication semiconductors and power semiconductors.
Yong-Jae Yu, https://orcid.org/0009-0007-2099-6107 received a B.S. from Pukyong National University, Department of New Materials and Systems Engineering, Busan, Korea, in 2018 and an M.S. from Pukyong National University, Department of Smart Green Technology Engineering in 2021. He is currently working as a researcher at KRIT, Jinju, Korea. His research interests include communication semiconductors, power semiconductors, and semiconductor materials.
Kyoung-Min Song, https://orcid.org/0009-0000-2485-0630 received a B.S. from Korea Aerospace University, Department of Electronic and Information Engineering, Seoul, Korea in 2015 and an M.S. from Korea Aerospace University, Department of Electronic and Information Engineering in 2018. He is currently working as a researcher at Hanwha Systems, Yongin, Korea. His research interests include spaceborne SAR, satellite AIT and micro-Doppler.