I. Introduction
Multi-band circuits employing millimeter waves (mmW) and up to the W-band (75–110 GHz) are attracting considerable interest owing to their potential in high-performance applications related to autonomous driving radars, high-speed mobile communications, imaging systems, and ultrafast wireless communications [1]. W-band communication and radar applications are mainly concentrated in two frequency bands (Band_L, 81–86 GHz; Band_H, 94–97 GHz). Accordingly, W-band low-noise amplifiers (LNAs) must be designed with broadband or multiband topology [1, 2].
However, in the case of mmW, as the frequency increases, the parasitic capacitance of transistors significantly deteriorate circuit performance. These degrade the operating frequency, maximum gain, and bandwidth, affecting system sensitivity and dynamic range. Therefore, mmW circuits generally use a neutralization technique that enhances performance by neutralizing the parasitic capacitance of transistors.
A neutralization technique mitigates the transistors’ parasitic capacitances, i.e., the gate-drain (Cgd) and drain-source (Cds) capacitances. Among the various neutralization techniques [3–6], the transformer-based feedback structure is more suitable for multiband circuits and mmW amplifiers [3]. This is implemented by reusing the input and output bias lines of the transistors. Thus, the performance is enhanced without any increase in the chip area or power consumption.
Unfortunately, neutralization techniques are not easily applied in the W-band. To apply neutralization technology in the W-band, it is essential to implement sufficiently small and high-quality capacitors. However, high-Q neutralization techniques are challenging to implement due to parasitic inductances generated by the capacitor itself and the circuit layout. Therefore, various previous studies have been reported to minimize unnecessary parasitic components using layout optimization and 3D electromagnetic simulation [7].
This paper presents a four-stage dual-band LNA monolithic microwave integrated circuit (MMIC) with a high-Q neutralization network designed and implemented based on a 0.1-μm gallium arsenide (GaAs) pseudomorphic high-electron-mobility transistor (pHEMT) process. Section II of this paper presents an analysis of the layout-optimized high-Q neutralization network in the W-band, a comparison with a typical structure, and the optimized structure design results. Section III derives the dual-band LNA design process. Section IV presents the experimental results of the four-stage dual-band LNA following the implementation of the optimized high-Q transformer neutralization structure. Finally, the conclusion and comparison with broadband topology LNAs are summarized in Section V.
II. W-Band LNA Circuit Design and Analysis
Fig. 1 shows the typical single-band and dual-band equivalent circuit schematics of the gate-drain transformer-based neutralization circuits, respectively. The transformer-based feedback neutralizes Cgd through mutual inductance. The simple neutralization condition is derived as a two-port network reverse admittance parameter, i.e., the imaginary part of Y12 is zero.
Thus, the simple coupled-line parameters of a transformer-based network can neutralize Cgd at the operation frequency. Single-band neutralization can be implemented as a simple first-order circuit, as shown in Fig. 1(a). However, for dual-band operations in the proposed LNA, the order of the neutralization network must be raised above the third order, which requires a high-order shunt capacitance, as shown in Fig. 1(b).
To realize the dual-band operation, the related matrix, equations, and the equivalent circuit shown in Fig. 2 are expressed in the transformer-based neutralization network, and those equations are well known as follows [8]. First, to simplify the transformer-base neutralization circuit analysis, the equivalent circuit components are assumed symmetric, LN1 = LN2 = LN, respectively. As shown in Fig. 2, the transformer-based neutralization network is composed of two coupled lines and a high-order shunt capacitance. They assume that the input voltages and currents are V1, V2, I1, I2, I3, and I4, respectively. The admittance parameter (Y-parameter) is used for analytical equation derivation owing to the one-stage of the LNA. For the reverse admittance derived, voltage, and current relation described, the overall input–output relation can be derived as follows:
The reverse admittance Y12=I1/V2|V1=0 is defined by detail expression as below:
From the neutralization condition Y12−sCgd = 0 (1), it can be rewritten as follows:
Near the transformer relation Leq = LN2/M−M,
k = M / L N L N
Again, letting S=jω, and to simply, since
L e q C g d = 1 / ω 0 2 L N C N = 1 / ω N 2
Assuming that ω0=ωN, the six-order polynomial equation can be rewritten as follows:
From the equation, its roots can be generalized as follows:
Now, by solving the six-order equation derived from the neutralization condition of the transformer-based neutralization equivalent circuit, we can obtain three positive solutions. The first two solutions, denoted as ωBand_L and ωBand_H, are located close to each other within the W-band of each band, while the last root, ωBand_3, is located out of the band. These three roots indicate that a simple transformer-based neutralization network consisting of two coupled lines and a high-order shunt capacitance can achieve neutralization at each band. Details are provided below:
Thus, implementing high-order shunt capacitance for dual-band operation is an important design parameter. However, in practice, parasitic inductance significantly reduces the reactance of the capacitor. As depicted in Fig. 1-(b), the following formula can be considered:
Fig. 3(a) and 3(b) show the typical and optimized layout structures, respectively, of the high-order shunt capacitance corresponding to Fig. 1(b). It comprises five components: the metal-insulator-metal (MIM) capacitor (CN1), back-via top metal (Lm1), bias to MIM metal connection (Lm3), MIM to MIM air-bridge metal (Lm2), and the back-via (LBV) structure, respectively. Note that the undesired parasitic inductances (Lpar: Lm1 + Lm2 + Lm3 + LBV) lower the Q-factor of the high-order shunt capacitance and drastically degrade the neutralization effect in the W-band.
First, to reduce parasitic inductances, Lm3 is included as the one MIM capacitor structure in the bias line of the neutralization network. However, Lm1 and LBV also induce undesired parasitic inductance, which makes it difficult to implement the desired small-value capacitor for high-order shunt capacitance.
Subsequently, it reduces the physical length of Lm1 to reduce Q-factor degradation. These are realized by reusing the top metal structure of the LBV for other MIM capacitor structures. The self-resonance frequency (SRF) of high-order shunt capacitance improvement and enhanced dual-band operation can be realized by reducing these parasitic inductances: (Lm1 + Lm3).
Fig. 4 shows the total parasitic inductances of the high-order shunt capacitance. In this sequence, the total parasitic inductance of the shunt capacitance is cut down from 37 pH to 23 pH in the optimized capacitance structure. Fig. 5(a) shows the Q-factor, which is enhanced over two times compared to the typical structure. Furthermore, Fig. 5(b) shows that the SRF of the optimized structure is 10% higher than that of the typical structure.
III. Dual-Band LNA Circuit Design
Sopt and Zopt (noise and gain circles) of the process are illustrated in Fig. 6. In the design of a one-stage LNA with input/output impedance matching network, it is essential to consider the placement of input and output stability circles in order to avoid unstable circuit areas. In the case of a dual-band LNA design, the impedance at each band is positioned closely together, leading to a more favorable trade-off between amplifier noise figure, gain, and input return loss.
Fig. 7 shows a comparison of the simulation results between a single transistor with the proposed transformer-based neutralization network and a transistor without it. The maximum available gain (MAG) of the transistor with neutralization applied in Band_L and Band_H demonstrates improvement compared to the case without neutralization. The neutralization effectively enhanced the gain performance in the target band while exhibiting some degradation in the other band, resulting in dual-band operation, as depicted in the overall MAG plot. The minimum noise figure is a slight degradation at the target frequency bands, even with the adaption of neutralization.
The four-stage cascade LNA structure was designed using a high-order transformer-based neutralization structure, as shown in Fig. 8. In the first stage, peak gains of 4.4 dB and 4.9 dB and noise figures of 3.7 dB and 3.8 dB are achieved in the lower-and upper-frequency bands (Band_L, 81–86 GHz; Band_H, 94–97 GHz), respectively. The subsequent stage is matched for the small noise contributions and optimized for each stage. The transformer-based neutralization network realized the gate and drain bias lines of the transistors by reusing them to reduce the chip area. The input and output matching networks were designed with a transformer structure and an open stub. As a simulation result, a four-stage LNA had a peak small-signal gain of 18.8 dB and 21.9 dB at the lower- and upper-frequency bands (at 84 and 96 GHz, respectively). The noise figures are 4.5 dB and 4.3 dB at each lower- and upper-frequency band. The transistor size is 2 × 25 μm at each stage. Capacitors were implemented by the MIM structure configuration, and the LBV structure described the GaAs process.
IV. Measurement Results
To verify the optimized neutralization technique, the W-band dual-band LNA was realized using a 0.1-μm GaAs pHEMT process with a 100-μm thick substrate. The chip photograph is shown in Fig. 9, with an overall chip size of 2.17 mm2, including the pads. A four-stage cascade LNA was measured using an on-wafer probe condition with W-band frequency extender modules.
Fig. 10 shows that the small signal gains are 20.3 dB and 21.7 dB at the lower- and upper-frequency bands, respectively. The measured input and output return losses were greater than 4 dB and 10 dB, respectively, in the overall bands, demonstrating broadband output matching. The noise figure was also measured using a noise figure analyzer (Keysight N8975A), a W-band block-down converter, and a W-band waveguide noise source (NoiseCOM NC5110A). The measured noise figures were 5.0 dB and 6.4 dB in the lower- and upper-frequency bands, respectively (Fig. 11). All passive components and structures were designed and optimized using an electromagnetic momentum simulation environment. The total drain current was 46 mA with 1 V VDD.
Table 1 summarizes the performance comparison of the W-band LNAs. This is compared to the results of a broadband LNA implemented in a GaAs pHEMT [9–13]. The various GaAs pHEMT W-band LNAs can be attributed to broadband topology. The measured dual-band LNA showed a similar performance as [10].
In this work, the parasitic inductances of high-order shunt capacitance were minimized by reusing the transistors’ bias lines as one capacitor and the top metal of the back via another capacitor. As a result, a high-Q transformer-based neutralization network was realized to connect each transistor structure, enhancing performance degradation in the W-band. Even though the performance was not superior to that of the broadband technique, the rejection of undesirable bands was observed in contrast to the broadband LNAs. Moreover, this is the first study that has attempted dual-band LNA among W-band GaAs pHEMT LNAs.
V. Conclusion
A dual-band LNA in the W-band was realized using an enhanced Q-factor transformer-based neutralization network with a gate-drain line feedback structure. The fabricated W-band dual-band LNA achieved dual-band LNA covering these two W-band frequency bands (Band_L, 81–86 GHz; Band_H, 94–97 GHz). Thus, dual-band LNA can be a competitive architecture in a W-band cooperative joint communication and radar application system.
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