### I. Introduction

*S*-parameter with the constant value. The proposed balun implemented using IPD technology to smaller and low loss.

### II. Design Theory and Simulation Results

### 1. Design Theory

_{1}, L

_{2}, C

_{1}, C

_{2}, and C

_{3}, which are from the distributed balun. Fig. 1(b) shows the proposed balun modified from Fig. 1(a). The left sides between Ports 1 and 2 are from the equivalent circuit of the low pass type, while the right sides between Ports 1 and 3 are from the circuit of the high pass type. The conventional circuit of Fig. 1(a) has a magnitude balance problem. To improve the magnitude balance, we add L

_{P}and C

_{P}parallel resonators at the center point of L

_{1}in the circuit where the C

_{2}and L

_{2}have been removed, as shown in Fig. 1(b). The half-point of the L

_{1}is where the values of L

_{2P}and L

_{1P}are the same. Similarly, we insert a parallel resonator at the doubling point of C

_{1}, where 2C

_{1}= C

_{1P}= C

_{2P}.

*Z*

_{0}, which is the ABCD parameter between Ports 1 and 2.

##### (1)

_{2}, B

_{2}, C

_{2}, and D

_{2}, as shown in Eq. (2). The input admittance Y

_{in}terminated as Y

_{0}at Port 3 in Fig. 1(b) is expressed as Eq. (3).

##### (2)

_{in}and A

_{1}, B

_{1}, C

_{1}, and D

_{1}parameters as Eq. (4).

_{T}= A

_{1}, B

_{T}= B

_{1}, C

_{T}= A

_{1}Y

_{in}+ C

_{1}, and D

_{T}= B

_{1}Y

_{in}+ D

_{1}. Using the relation between the

*S*-parameter and the ABCD parameter,

*S*

_{21}is obtained as Eq. (5).

*S*

_{21}|, the derived |

*S*

_{21}| must be frequency independent in terms of the frequency over a wide bandwidth. The differential value of the derived |

*S*

_{21}| at the center frequency

*ω*

_{0}is zero to make the frequency-dependent term reduced in wideband; then the value of L

_{P}is expressed as Eq. (7).

_{P}of the inserted parallel resonant values are derived from the resonant circuit.

### 2. Circuit Simulation Results

### III. 3D Structure and Fabrication Results

_{1}(Metal1) and M

_{3}(Metal3) layers and is implemented in the form of a spiral inductor using M

_{1}of the SiN

_{2}layer. Then, the M

_{1}and M

_{3}layers are connected using the SNO

_{2}(SiN open) metal layer penetrating the SiN

_{3}dielectric (DE) layer. The capacitor uses M

_{2}and M

_{3}layers and is implemented in the form of a metal-insulator-metal (MIM) capacitor by inserting a SIN

_{3}DE layer between the metals. A DE layer is inserted between each metal layer of the inductor and capacitor to prevent short circuits. Table 2 shows the details of the layers used in the structure of Fig. 3.