A Single-Stage 12-Times Frequency Multiplier for a 5G Frequency Synthesizer

Article information

J. Electromagn. Eng. Sci. 2022;22(3):302-308
Publication date (electronic) : 2022 May 31
doi : https://doi.org/10.26866/jees.2022.3.r.91
Department of Electrical Engineering, Kookmin University, Seoul, Korea
*Corresponding Author: Junseok Park (e-mail: jspark@kookmin.ac.kr)
Received 2021 June 20; Revised 2021 October 26; Accepted 2022 March 3.

Abstract

This paper presents a single-stage 12-times frequency multiplier composed of an invented harmonic generator (HG) and a modified cascode buffer. The reliable output frequency band is guaranteed from 16 GHz to 28 GHz (54.5% frequency range). The whole band is divided to 256 subsidiary frequency bands by applying 8-bit digitally controlled capacitor banks of LC (inductor and capacitor)-tuned output. The invented HG architecture is based on a double-balanced mixer, but the bottom and top differential pairs are appropriately biased to generate the required turn-on time, τ, for obtaining the more dominant desired 12th harmonic. In addition, to reduce power consumption and conversion gain variation for the target frequency band, a negative-gm differential pair is added to the HG core in parallel to enhance the equivalent parasitic resistance, which is directly proportional to the HG gain. Newly created automatic constant amplitude control is able to keep the HG amplitude output constant as well as keep it from oscillating. Further desired harmonic amplification and unwanted suppression can be achieved by the proposed cascode buffer. The proposed 12-times multiplier is fabricated on a 65-nm CMOS (complementary metal-oxide-semiconductor) process and successfully tested. Chip die size is 0.4 mm2, and power consumption is only 4 mW.

I. Introduction

For the last decade, sub-sampling phase-locked loop (SSPLL) and injection-locked phase-locked loop (ILPLL) have been actively researched to suppress in-band phase noise by N2 when transferred to PLL outputs [14], where N is the division number in the feedback path in Fig. 1(a). However, applying SSPLL and ILPLL at the millimeter wave (mm-wave) causes some significant problems. Because sub-sampling phase detectors (SSPD in Fig. 1(b)) and pulse width controls (PWC in Fig. 1(c)) are directly connected to the voltage-controlled oscillator (VCO) and injection-locked VCO (ILVCO), they consume lots of power and cause series spurs.

Fig. 1

PLL structures: (a) charge pump, (b) sub-sampling, and (c) injection-locked.

Due to the low quality-factor of capacitors in mm-wave and CMOS (complementary metal-oxide-semiconductor) flicker noise, the phase noise of CMOS VCO is very poor and consumes a lot of power. Instead of running VCO at mm-wave, various combined structures of lower frequency SSPLL or ILPLL and following frequency multipliers have been preferred [59].

As shown in Fig. 2(a), a tuned-frequency multiplier (TFM) generally consists of a harmonic generator (HG), a band-pass filter (BPF), and an amplifier. Overdriving an amplifier generates weak higher harmonics of the fundamental tone and the desired harmonic is conserved by a simple BPF, such as a LC (inductor and capacitor) resonant tank. An additional LC-tuned amplifier is usually used to achieve a suitable amplitude to drive the next stage and suppress unwanted harmonics. While a TFM is the simplest frequency multiplier, it suffers from unwanted harmonics. Particularly, harmonic rejection of the fundamental tone is relatively poor [9]. A more efficient method of performing better harmonic suppression is to inject high harmonics into a free-running oscillator (Fig. 2(b)). An injection-locked frequency multiplier (ILFM) is able to suppress harmonics significantly by forcing oscillation at the desired harmonic, but it suffers from a limited injection-locking range, and additional error-correcting feedback circuitries are mostly required to secure a reliable operable frequency range [10]. A multi-phase-based topology (Fig. 2(c)) frequency multiplier can be considered a candidate [11], but output frequency accuracy directly depends on phase-shifting accuracy, which might shift due to PVT (process, power supply voltage, and temperature) variations without a phase-error correcting loop.

Fig. 2

Frequency multiplier block diagram: (a) tuned-amplifier, (b) injection-locked, and (c) multi-phase.

In this paper, we present a single-stage 12-times frequency multiplier which is based on TFM topology. To the best of our knowledge, no other published papers have achieved a more than 4-times mm-wave frequency multiplier using one stage; rather, they have used more than two cascade stages, such as 2-times plus 4-times, resulting in 8-times frequency multipliers. This paper’s ultimate goal is to provide an efficient mm-wave frequency multiplier solution for a 5G frequency synthesizer. This paper is organized as follows. In Section II, the proposed 12-times frequency multiplier structure is introduced. In addition, the methods of optimizing conversion gain variations and a harmonic rejection ratio (HRR) for the target frequency band are described. Section III shows the chip fabrication and measurement results. A comparison of this study with other recently published frequency multipliers is provided in Table 1 [1114]. A summary and conclusion are reported in Section IV.

Comparison with published frequency multipliers

II. 12-Times Frequency Multiplier Design

Fig. 3 shows the proposed 12-times frequency multiplier block diagram. It is composed of a modified double-balanced mixer (DBM)-type HG and a modified cascode buffer with constant-gm, proportional absolute temperature (PTAT) current references, and an automatic constant amplitude loop (ACAL).

Fig. 3

Proposed 12-times frequency multiplier block diagram.

1. Proposed 12-Times Harmonic Generator

The detail circuit schematic of the proposed 12-times HG is shown in Fig. 4. The circuitries inside the dotted box are a modified DBM. If VpVn is big enough to turn M1M6 on and off completely, the corresponding differential current, IT, can be expressed as

Fig. 4

Proposed 12-times frequency harmonic generator.

(1) IT=(IM3-IM4)IM1+(IM6-IM5)IM2,

where IM1IM6 are bias currents when M1M6 are turned on. The differential currents of the top pairs are

(2) IM3-IM4=4πn=11nsin (nπ2)cos(ωnt)IM6-IM5=-4πn=11nsin (nπ2)cos(ωnt).

The currents of M1 and M2 are

(3) IM1=Idc2+2Idcπk=11ksin (kπτT)cos(kωt)IM2=Idc2+2Idcπk=11ksin (kπτT)cos(kωt+kπ),

where Idc is the dc bias current, τ is the turn-on time, and T is the period of the applied first fundamental. Setting τ = T/24 in Eq. (3), Eq. (1) is re-arranged as

(4) IT=β2cos(2ωt)+β4 cos(4ωt)+β6 cos(6ωt)+β8 cos(8ωt)+β10 cos(10ωt)+β12 cos(12ωt)+β14 cos(14ωt)+,

where β2β14 are the calculated current coefficients, the values of which are:

(5) β2=3.13,   β4=3.25,   β6=3.12,   β8=2.76,β10=2.74,   β12=2.5,   β14=2.25,

The current coefficient at the 12th harmonic is not dominant, but 20log (β4/β12) is only 2.3 dB, which can be easily overcome by the LC resonated at the 12th harmonic.

The output impedance is the LC bank, the states of which are controlled by 8 digital bits. The C bank is binary weighted as C8 = 2C7 = 22C6 = 23C5 = 24C4 = 25C3 = 26C2 = 27C1. As a result, the target frequency band from 16 GHz to 28 GHz is divided into 256 sub-frequency bands. The resonant frequency at each state can be represented as follows:

(6) fres=12πL(k=18CkDk+k=18(CkCdkCk+Cdk)Dk¯),

where Dk is the kth capacitor digital control bit, which is either 1 or 0, Dk¯ is the complement of Dk, and Cdk is the total parasitic capacitance between the drain node of the Mk switch and ground. As the turn-on switch number increases, the parasitic parallel resistance, RP, in Fig. 4 will decreased, as shown in Fig. 5. Therefore, the resonant amplitude will vary for the different C-bank states. To maintain the same amplitude, the ITRP product needs to be constant. Therefore, IT should be increased for a small RP, which not only causes the power consumption to increased but also makes the required input amplitude bigger than before. Instead, a negative-gm pair is added to the main core in parallel. The equivalent resistance of a parallel RP and −2/gm in Fig. 4 can be expressed as

Fig. 5

Capacitor bank Ron (device-on resistance) C series-to-parallel impedance transformation.

(7) Req=HRp2(H-1)Rp=(HH-1)RP,H>1,

where H = 2/(gmRp). For example, Req will be three times that of Rp when H = 1.5, with a smaller current for the added negative-gm pair than the IT required to maintain the output amplitude. The negative-gm is able to improve the HRR performance [10]. Parallel RLC impedance, ZRLC(ω), is expressed as

(8) ZRLC(ω)=1(1Rp)2+(1ωLP-ωCp)2.

The HRR in dB, HRRdB(ω0 ± Δω), at Δω from the resonant frequency, ω0 is defined as the dB expression of the ratio of the impedance at ω0 and ω0 ± Δω, which can be derived as

(9) HRRdB(ω0+Δω)=20log(Rp)+10log [1Rp2+(1(ω0±Δω)Lp-(ω0±Δω)Cp)2].

Replacing Rp with (H/H – 1)Rp into Eq. (9), then Eq. (9) can become

(10) HRRdB(ω0±Δω)|RpRpHH-1=20log(Rp)+20log(HH-1)+10log [1(HH-1)2Rp2+(1(ω0±Δω)Lp-(ω0±Δω)Cp)2].

The HRR improvement, HRIdB gm, can be defined by subtracting Eq. (9) from Eq. (10):

(11) HRRIdB-gm=20log(HH-1)+10log[(K-1K)2+Rp2Y21+Rp2Y2]

where

(12) Y=1(ω0±Δω)LP=(ω0±Δω)Cp.

For example, for ω0 = 2π (27.96 GHz), Δω = 2π (2.33 GHz), Lp = 298 pH, Cp = 108 fF, and Rp = 1,500 Ω HRRdB = 13 dB in Eq. (10) and HRIdB gm = 20 dB in Eq. (11) when H = 1.2. Consequently, HRRdB at 2π (30.29 GHz) is 33 dB with the negative-gm pair.

2. The Buffer with Constant Output Amplitude Control

As shown in Fig. 6, we used the same cascode buffer topology in [10] to get more HRR and low power consumption, but we inserted a dc-blocking capacitor, Cc, for better power optimization, as shown in Fig. 6. By applying an appropriate Cc size, the load of the negative-gm pair can be reduced. So, there is room to increase the M6 and M7 device size to maintain the same load as before, which leads the corresponding transconductance, gm, to increase with the constant current, Itail, because the overdrive voltage, (VgsVth), is decreased. The buffer is composed of a typical cascode buffer, a negative-gm pair, and an automatic amplitude control loop (AACL). Just like the proposed HG, the buffer output of the LC-bank resonant is programmed by 8 digital bits. The equivalent parallel of the LC-bank resistance can be also manipulated by the positive feedback pair transconductance, gm, as in Eq. (7).

Fig. 6

Proposed cascode buffer with automatic amplitude control loop.

For the buffer output, Vout, the peak is detected though the RF peak detector. The Vpeak is compared with the Vref. If Vpeak > Vref, VI is increased to reduce Iref. Consequently, Itail is decreased so the transconductance, gm, of the M6 and M7 pair results in the reduction of Req in Eq. (7), which is proportional to the output amplitude. Similarly, when Vpeak > Vref, the output amplitude is reduced. Therefore, the AACL is able to help to keep a constant amplitude within 1 dB for a 6 dB input and the mentioned PVT variations.

Fig. 7 shows the proposed 12-times frequency multiplier output power simulation when the output power is 1.42 dBm and the worst harmonic rejection is 51.71 dBc.

Fig. 7

Proposed 12-times frequency multiplier output power simulation.

III. Fabrication and Measurement

The prototype of the proposed 12-times frequency multiplier is fabricated on 65 nm CMOS technology and its size is 0.4 mm2, as shown in Fig. 8. The laboratory test environment is shown in Fig. 9.

Fig. 8

Photograph of the proposed 12-times frequency multiplier.

Fig. 9

Test environment setup.

The harmonic measurements are shown in Fig. 10, where the worst harmonic rejection ratios are −50.1 dBc and −51.66 dBc on 15.96 GHz and 27.96 GHz, respectively. Fig. 11(a) shows the measurement of output power versus output frequency. The 12-times frequency multiplier output powers at 15.96 GHz and 27.96 GHz are −2.03 dBm and −1.94 dBm, respectively. The worst harmonic suppression versus output frequency is shown in Fig. 11(b), where the maximum harmonic suppression of the frequency multiplier is 51.5 dBc at 27.96 GHz. When compared with the simulation results, almost similar measurement results are obtained. The phase noise degradation due to the proposed multiplier is measured. As shown in Fig. 12, only 0.1 dB phase noise is added when compared with the mathematical phase noise degradation (20log (12) = 21.6 dB).

Fig. 10

Harmonic measurement of (a) 15.96 GHz and (b) 27.96 GHz.

Fig. 11

Measurement of (a) output power and (b) harmonic suppression versus output frequency.

Fig. 12

Phase noise measurement of input versus output.

Table 1 presents a summary of recently published papers on mm-wave frequency multipliers, including the multiplier proposed in this paper. The proposed multiplier has better frequency range percent and power consumption performances. However, the multiplier used in [12] and [14] has a better harmonic rejection ratio because the proposed multiplier has a much bigger multiplication factor (12 vs. 3). To achieve a fair comparison, figure-of-merit (FoM) is calculated for each paper. The proposed multiplier achieves the best FoM among them.

The measurement results of the power consumptions for different frequencies and the output powers at different input powers when disabling AACL are summarized in Table 2.

Summarized frequency multiplier measurement results

IV. Summary and Conclusion

This paper proposed an unconventionally created frequency mm-wave HG based on a Gilbert cell DBM structure with a positive feedback pair. The nonlinear switching behaviors of a Gilbert cell’s top differential pair and bottom differential pairs create strong harmonics of double frequency of the fundamental tone. The consequent adjacent harmonics difference is twice the fundamental tone, which makes it easier to suppress unwanted harmonics. By adjusting a device’s turn-on time, τ, the current coefficient at the desired 12th harmonic can be improved. Furthermore, with the help of negative-gm, the proposed 12-times HG consumes only 4 mW. Since the HG is in the middle of a 5G synthesizer, one of 256 different frequency bands can be simultaneously programmed when the synthesizer frequency is digitally programmed. Consequently, a 54.5% frequency range is accomplished by 8-bit capacitor banks.

The cascode buffer proposed in this paper is able to suppress undesired harmonics further by applying an adequate current to a negative-gm pair and a PTAT reference current for each sub-frequency band to achieve more than 50 dBc harmonic rejection. Also, a newly adapted ACAL helps to reduce the output power variation to within 1 dB for PVT variation (±3σ process, ±10% power supply voltage, and temperature from −20°C to 100°C).

Acknowledgments

This work was supported by an Institute of Information & Communications Technology Planning & Evaluation (IITP) grant funded by the Korean government (MSIT) (No. 2020-0-00216, Development of mm-Wave data conversion free Phased-Array Tx based on 6PMP). The Eda tool was supported by the IC Design Education Center (IDEC), Korea.

References

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Biography

SungWoo Im received his B.S. and M.S. from Dongguk University in 2004 and 2007, respectively, and his Ph.D. in electronics engineering from Kookmin University, Seoul, South Korea, in 2021. He is currently a staff of Yang, jung sook(member of national assembly). His research interests include the RF/microwave/mm-wave communication system.

JunSeok Park received his B.S., M.S., and Ph.D. degrees in electronics engineering from Kookmin University, Seoul, South Korea, in 1991, 1993, and 1996, respectively. In 1997, he was a senior researcher in the Department of Electrical Engineering at the University of California at Los Angeles (UCLA). From 1998 to 2003, he was an assistant professor in the Information Technology Engineering Division at Soonchunhyang University, Asan, South Korea. He is currently a professor in the Department of Electrical Engineering at Kookmin University. His research interests include the RF/microwave/mm-wave/THz SoC and MMIC, numerical methodology for integrated metamaterial applications, EBG, DGS, solid-state ground configuration and optimization, low-noise phased array for military/automotive radar systems, and uniform smart RF signal/power circuits driven by machine learning.

KyuHyun Nam received his B.S., M.S., and Ph.D. degrees in electrical engineering from Kookmin University, Seoul, South Korea, in 2012, 2014, and 2022, respectively. He is currently a post-doctoral research fellow in electronics engineering at Kookmin University, Seoul, South Korea. His research interests include the RF/microwave/mm-wave communication system.

Article information Continued

Fig. 1

PLL structures: (a) charge pump, (b) sub-sampling, and (c) injection-locked.

Fig. 2

Frequency multiplier block diagram: (a) tuned-amplifier, (b) injection-locked, and (c) multi-phase.

Fig. 3

Proposed 12-times frequency multiplier block diagram.

Fig. 4

Proposed 12-times frequency harmonic generator.

Fig. 5

Capacitor bank Ron (device-on resistance) C series-to-parallel impedance transformation.

Fig. 6

Proposed cascode buffer with automatic amplitude control loop.

Fig. 7

Proposed 12-times frequency multiplier output power simulation.

Fig. 8

Photograph of the proposed 12-times frequency multiplier.

Fig. 9

Test environment setup.

Fig. 10

Harmonic measurement of (a) 15.96 GHz and (b) 27.96 GHz.

Fig. 11

Measurement of (a) output power and (b) harmonic suppression versus output frequency.

Fig. 12

Phase noise measurement of input versus output.

Table 1

Comparison with published frequency multipliers

This work Chan and Long [11] Shirazi et al. [12] Zong et al. [13] Fan et al. [14]
Technology (nm) 65 90 130 40 65
Frequency (GHz) 15.96–27.96 56–65 52.8–62.5 48.4–62.5 54.9–63.5
Frequency BW (%) 54.5 14 16.8 25.4 14.5
Power (mW) 4 9.6 7.6 24 9
Maximum spurs (dBc) 50.1 N/A 55 45 61
Multiplication 12 3 3 3 3
Output power (dBm) −2 −27 −28 −2.48 −11
Phase noise (dBc/Hz) @ 1 MHz −120.2 −113 −102.4 −100.08 −100.7
Area (mm2) 0.4 0.8 0.2 0.13 0.12
FoM −72.2 N/A −63.2 −50.0 −67.8

Table 2

Summarized frequency multiplier measurement results

Frequency (GHz)

15.96 19.92 24 27.96
Supply voltage (V) 1.2 1.2 1.2 1.2
Total current (mA) 3.9 3.5 3.1 2.9
Power consumption (mW) 4.68 4.2 3.72 3.48
Output power (dBm)
 At 0 dBm input −2.03 −1.96 −2.01 −1.94
 At −5 dBm input −7.21 −6.82 −7.14 −6.87
 At −10 dBm input −12.11 −12.01 −12.41 −11.72