| CMOS 120 GHz Phase-Locked Loops Based on Two Different VCO Topologies |
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Junghwan Yoo, Jae-Sung Rieh |
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School of Electrical Engineering, Korea University |
Correspondence:
Jae-Sung Rieh,Email: jsrieh@korea.ac.kr
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| Abstract |
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This work describes the development and comparison of two phase-locked loops (PLLs) based on a 65-nm CMOS technology. The PLLs incorporate two different topologies for the output voltage-controlled oscillator (VCO): LC cross-coupled and differential Colpitts. The measured locking ranges of the LC cross-coupled VCO-based phase-locked loop (PLL1) and the Colpitts VCO-based phase-locked loop (PLL2) are 119.84-122.61 GHz and 126.53-129.29 GHz, respectively. Th e output powers of PLL1 and PLL2 are -8.6 dBm and -10.5 dBm with DC power consumptions of 127.3 mW and 142.8 mW, respectively. Th e measured phase noise of PLL1 is -59.2 at 10 kHz offset and -104.5 at 10 MHz offset, and the phase noise of PLL2 is -60.9 dBc/Hz at 10 kHz offset and -104.4 dBc/Hz at 10 MHz offset. The chip sizes are $1,080{mu}m{times}760{mu}m$ (PLL1) and $1,100{mu}m{times}800{mu}m$ (PLL2), including the probing pads. |
| Key words:
CMOS, Frequency Doubler, Phase-Locked Loop (PLL), Signal Source, Voltage-Controlled Oscillator (VCO) |
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